外文翻譯---硬件軟件的設(shè)計(jì)和開發(fā)過程-wenkub
2023-06-16 15:44:51 本頁(yè)面
【正文】 fication activities. Certainly the advancements in embedded software tools such as static code checkers, debuggers and hardware emulators have helped to solve some of the software verification problems, but software verification activities have bee more time and resource consuming than the actual software creation. Timetomarket constraints have pushed software verification activities to the systemlevel, and led to a greater demand for production hardware to be made available earlier in the software development flow. As with the software case, the semiconductor design munity has made a very similar transformation in their design and verification strategies sparked by advances in the EDA munity. Designs that were once implemented pletely at the transistor level migrated to the gatelevel implementation through the development of schematic capture tools. The creation of hardware description languages such as Verilog and VHDL and the corresponding pilers, simulators and synthesis tools allowed hardware designers to move away from the gatelevel implementation to the register transfer level (RTL). The EDA munity is now promoting even higher levels of abstraction, often under the banner of electronic system level design (ESL) . Again, this represented a fundamental change in design abstraction, which allowed the designers to think in terms of overall functionality instead of the configuration of gates needed to implement the desired functionality. As Application Specific Integrated Circuit (ASIC) design plexities have grown and the process geometry continued to shrink, the manufacturing and NRE costs for silicon has increased rapidly. For example, the cost for silicon mask sets range from $50,000 for a simple ASIC to greater than $1,000,000 for an advanced microprocessor or microcontroller . The high costs associated with ASICs underscores the motivation of the hardware munity to insure that the intended functionality is implemented correctly prior to taking a design to silicon. The EDA industry has helped this cause by providing sophisticated verification tools that prove the highlevel design and the silicon implementation will function equivalently. However, even with these tools available, more than 189。一些系統(tǒng)如照像手機(jī)和掌上電腦等等都變成了現(xiàn)實(shí)。這種集合語(yǔ)言的創(chuàng)造使得程序員能夠高于機(jī)器語(yǔ)言進(jìn)行編程，提高了代碼生成和歸檔的效率。相反，隨著集成系統(tǒng)的特征更為豐富，操作系統(tǒng)的復(fù)雜性和相應(yīng)功能迅速增加，同時(shí)軟件的應(yīng)用和檢驗(yàn)的消耗也增加 。通過開發(fā)圖解抓取工具將一度應(yīng)用于晶體管層面上的設(shè)計(jì)提升到了門類應(yīng)用層面上。 隨著應(yīng)用特定集成電路設(shè)計(jì)的復(fù)雜性不斷提高，而設(shè)計(jì)的體積又在不斷縮小，硅片的制造成本也上升得很快。然而，即使能獲得這些工具，仍有超過二分之一的集成電路設(shè)計(jì)和 ASIC 設(shè)計(jì)在運(yùn)用時(shí)需要硅片返工。當(dāng)今的系統(tǒng)設(shè)計(jì)過程包括硬件結(jié)構(gòu)、所需功能 性、微處理器的生產(chǎn)量、存儲(chǔ)器結(jié)構(gòu)以及潛在硬件遷移路徑的書面研究。 這篇論文通過創(chuàng)造一個(gè)虛擬系統(tǒng)，為系統(tǒng)層面的設(shè)計(jì)提供了一個(gè)新的方法。因此，通過去除重復(fù)工作、提高最后系統(tǒng)的質(zhì)量、提升監(jiān)測(cè)能力和縮短市場(chǎng)的實(shí)時(shí)性來提高生產(chǎn)力。例如，有一個(gè)二維的結(jié)構(gòu)空間，其中的兩個(gè)設(shè)計(jì)參數(shù)（顯然當(dāng)中有很多的參數(shù)）分別為能量消耗和時(shí)鐘速度，理想的解決方法被列在了指標(biāo)的中央。 相反，綠色的十字顯示得到最佳設(shè)計(jì)方法的另一條路。 基于模型的方法建議使用結(jié)構(gòu)探尋的工具來加快對(duì)各種中央處理器、存儲(chǔ)器和外圍組件即系統(tǒng)結(jié)構(gòu)組件的研究。其目的是通過評(píng)價(jià)不同的結(jié)構(gòu)和分隔選項(xiàng)得到最佳設(shè)計(jì)的第一個(gè)近似方案。正如這篇論文所提出的，在模擬仿真的正確性、模型制作的成 本和制作新模型的時(shí)間上存在相互交換。 讓我們把目光集中在左下方的框架，這里顯示的是對(duì)虛擬系統(tǒng)的一個(gè)高度精確和快速的仿真，稱之為準(zhǔn)確循環(huán)仿真。模型和指標(biāo)可以決定最佳的設(shè)計(jì)方法。 仿真速度和準(zhǔn)確性 在我 們討論系統(tǒng)之前，提供一些背景資料非常重要，這些資料說明了模型抽象的層面以及它們自身是如何進(jìn)行最好的應(yīng)用的。 。功能模型執(zhí)行重要指令的速度要快于在轉(zhuǎn)換中運(yùn)用的模型。 32字節(jié)的 CPU虛擬處理器模型可以加載和激勵(lì)用于傳統(tǒng)工作臺(tái)開發(fā)的可執(zhí)行圖像。隨著其他 模型的制成，這些
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