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2025-05-16 15:44 本頁(yè)面
【正文】 rom the gatelevel implementation to the register transfer level (RTL). The EDA munity is now promoting even higher levels of abstraction, often under the banner of electronic system level design (ESL) . Again, this represented a fundamental change in design abstraction, which allowed the designers to think in terms of overall functionality instead of the configuration of gates needed to implement the desired functionality. As Application Specific Integrated Circuit (ASIC) design plexities have grown and the process geometry continued to shrink, the manufacturing and NRE costs for silicon has increased rapidly. For example, the cost for silicon mask sets range from $50,000 for a simple ASIC to greater than $1,000,000 for an advanced microprocessor or microcontroller . The high costs associated with ASICs underscores the motivation of the hardware munity to insure that the intended functionality is implemented correctly prior to taking a design to silicon. The EDA industry has helped this cause by providing sophisticated verification tools that prove the highlevel design and the silicon implementation will function equivalently. However, even with these tools available, more than 189。 of all IC and ASIC designs require a respin of silicon, where 70% of the respins are due to logic or functional errors that verification efforts should have caught . With the huge investment required for each respin, system level verification is being a focus of the overall hardware verification strategies. Although we have seen significant advancements in the processes of hardware and software design during the past two decades, surprisingly, there have been little advancements made at the system level. Today’s system process consists of the paper study of the proposed hardware architecture, required functionality, microprocessor throughput, memory configuration, and the potential hardware migration paths. The process has remained relatively unchanged. Furthermore, the software implementation is typically held off until hardware prototype units are created, placing the software developers and system verification teams at a disadvantage. This current approach has many drawbacks including: slow adaptation to changes in customer requirements, drawn out hardware and software integration, limitations in system debugging, and difficulties meeting the timetomarket constraints. This paper presents a new approach to systemlevel design through the creation of a virtual system, which allows for an early analysis of hardware and software interaction while removing many of the drawbacks plaguing traditional system development. This paper also presents a virtual automotive airbag system implementation and explores the benefits of virtual system development. PARADIGM SHIFT The motivation for system level design and analysis is to significantly improve productivity through a paradigm shift that allows hardware and software to be designed concurrently rather than serially. Productivity is thus enhanced by the elimination of rework, increased quality of the final system, improved verifi
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