【正文】 iples: first, the revised capacity (a wide depth) is not greater than 18k bit。 In order to apply munications bus and interface standards, many highend FPGA internal are integrated strings and transceiver (SERDES), can achieve dozens of Gbps speed of delivery. The highend product not only Xilinx pany has integrated Power PC series CPU, still embedded with DSP Core modules, its corresponding systemlevel design tools are EDK and Platform, according to this Studio forward Chip System (System on the concept of Chip cluster generator attempts. Through Miroblaze, Picoblaze PowerPC, such as the platform, can develop standards and its associated applications DSP . The FPGA design precautions： Whether you are a logical designers, hardware engineer or system engineer, or even with all these titles, as long as you in any kind of highspeed and more plex systems use agreement the FPGA, you will probably need to resolve device configuration, power management, IP integration, signal integrity and some of the other key design issues. However, you don39。 The fourth category is distributed wiring resources, used for proprietary clock and reset the control signal. In practice, designers don39。 x老師的熱心給予的完成畢業(yè)設(shè)計(jì)的動(dòng)力， x老師的幫助使我客服了諸多困難，最終在老師的指導(dǎo)下我完成了畢業(yè)設(shè)計(jì)，再次我要深深的感謝她。 當(dāng)然在設(shè)計(jì)過程中也遇見了不少自己解決不了的問題，對(duì)此我很感謝我的老師、同學(xué)們的幫助。這次畢業(yè)設(shè)計(jì)可以說是對(duì)四年的大學(xué)學(xué)習(xí)的總結(jié)。 畢業(yè)設(shè)計(jì)（論文）專用紙 第 頁 8 畢業(yè)設(shè)計(jì)（論文）專用紙 第 頁 9 第 4章 模擬仿真 年月日模塊仿真 該仿真圖顯示的是 09年 5月分的，由圖可以看出 5月分有 31天，當(dāng)月份進(jìn)入到下一個(gè)月的時(shí)候，日期 day則變?yōu)?1號(hào)，仿真結(jié)果無誤。這里不再多說。 年月日模塊（ nyr2021） 日計(jì)數(shù)：日信號(hào) qr[7:0]，日進(jìn)位信號(hào) clky，以及每月天數(shù) date。 如果 qfh5， qfl==9，則 qfh=qfh+1， qfl=0， carry1=0；如果 qfh5， qfl9，則 qfh=qfh， qfl=qfl+1，carry1=0。給予秒信號(hào)和進(jìn)位信號(hào)一個(gè)初始值，令 {qmh,qml}=0,carry1=0。 系統(tǒng)設(shè)計(jì)圖 圖 1 流程圖 畢業(yè)設(shè)計(jì)（論文）專用紙 第 頁 4 圖 2 功能設(shè)計(jì)圖 畢業(yè)設(shè)計(jì)（論文）專用紙 第 頁 5 第 3章 各功能模塊介紹 分頻模塊（ fenpin） 該模塊的主要功能是想得到一個(gè)時(shí)鐘頻率為 1Hz的一個(gè)脈沖，也就是說 想得到周期為 1秒的一個(gè)脈沖。 FPGA簡介 FPGA 是現(xiàn)場可編程門陣列（ Field programmable gates array）的英文簡稱，是由可編程邏輯模塊組成的數(shù)字集成電路（ IC） ,這些邏輯 模塊之間用可配置的互聯(lián)資源。采用 FPGA設(shè)計(jì)的萬年歷由于成本低，精度高，可靠性好 等優(yōu)點(diǎn)，使它有了非常廣闊的使用之處。每到新年，人們就會(huì)買來一本新的日歷，配上繪有圖畫的日歷牌掛在墻上，既是裝飾，又能指示年、月、日、星期等信息。 進(jìn)入信息時(shí)代，時(shí)間觀念越來越重，但是老式的鐘表以及日歷等時(shí)間顯示工具已經(jīng)不太適合。各個(gè)模塊完成不同的任務(wù)，合在一起就構(gòu)成了萬年歷的系統(tǒng)電路設(shè)計(jì)。例如：在萬年歷上添加鬧鐘，同時(shí)顯示陰陽歷等。對(duì)此國內(nèi)外許多設(shè)計(jì)人員對(duì)其進(jìn)行了大量的設(shè)計(jì)，有用單片機(jī)開發(fā)的，有用 FPGA開發(fā)的。數(shù)字萬年歷 從原理上 講是一種典型的數(shù)字電路，其中包括了組合邏輯電路和時(shí)序電路。由于 FPGA 的設(shè)計(jì)成本低廉，修改方便，從而催生了的、許多富有創(chuàng)新意識(shí)的公司，這就意味著設(shè)計(jì)人員可以在基于 FPGA 的測試平臺(tái)上實(shí)現(xiàn)他們的軟件開發(fā)，而不需要承擔(dān)數(shù)額巨大的不可重現(xiàn)工程的成本或昂貴的開發(fā)工具。 時(shí)間顯示調(diào)整模塊（ mux_4） 該模塊的功能是控制顯示器，決定顯示年月日還是時(shí)分秒。給予初始值： {qfh,qfl}=8’ h00,進(jìn)位信號(hào) carry1=0。amp。對(duì)于日信號(hào)，當(dāng) qr=date時(shí)，則令 qr=1， clky=1；否則若日信號(hào)的十位與 date的十位相同且個(gè)位小于 date的個(gè)位，則十位不變，個(gè)位每個(gè)脈沖加 1（這里的秒沖有外界和內(nèi)部兩種，內(nèi)部脈沖來自時(shí)分秒模塊的輸出 cout）；若日信號(hào)十位小于 date的十位，但是個(gè)位相等，則令十位加 1，個(gè)位計(jì)為 0；若 日信號(hào)十位和個(gè)位均小于 date則令日信號(hào)十位不變，個(gè)位加 1。 譯碼器（ yimaqi） 譯碼器可以將輸入代碼的狀態(tài)翻譯成相應(yīng)的輸出信號(hào)，以高、低電平的形式在各自的輸出端口送出，以表示其意愿。與傳統(tǒng)紙質(zhì)的萬年歷相比 ,數(shù)字萬年歷得到了越來越廣泛的應(yīng)用。在這次的設(shè)計(jì)過程中主要 是在 Quartus2上使用 Verilog語言完成代碼的編寫與模擬仿真，在設(shè)計(jì)過程中出現(xiàn)了不少的問題，一些問題是因?yàn)樽约旱拇中拇笠?，也有一些問題則是對(duì)相關(guān)知識(shí)的認(rèn)識(shí)不夠徹底。畢業(yè)設(shè)計(jì)是對(duì)大學(xué)以往知識(shí)的綜合運(yùn)用，但是由于學(xué)習(xí)的不夠認(rèn)真，導(dǎo)致這設(shè)計(jì)過程中遇見了很多看似簡單卻沒法自我完成的問題。 Secondly, a wide cannot exceed 36 biggest bits. Of course, can be more pieces of block RAM cascade up to form larger RAM, now only limited by the number of RAM chip inside block, and no longer subject to two above principle constraint. 5. Rich wiring resources Wiring resources connected all the units inside the FPGA, and the length of the attachment and process determines the signal on the wire transmission speed and driving 畢業(yè)設(shè)計(jì)（論文）專用紙 第 頁 18 ability. The FPGA chip has a wealth of wiring resources inside, according to the process, length, width and distribution in different position and are divided into four kinds of different categories. The first kind is global wiring resources, used for chip inside global clock and global reset/buy a wiring。t have to face these challenges alone, because in the current leading FPGA pany application engineers every day to solve these problems, and they have put forward some amaze your design work easier design guiding principles and solutions. The I/O signal distribution Can provide the most multifunctional pins, I/O standards, termination scheme and difference right FPGA in signal distribution are the most plex design guiding principles. Although the Altera FPGA device no design guiding principles (because it realize rise pare easy), but the spirit of the FPGA design principles guiding thought is quite plex. But in either case, for I/O pins distribution, there are some signal to keep in mind is mon steps: 1. Use an electronic data list all plans signal allocation, and their important properties, such as I/O standard, voltage, need termination methods and relevant clock. 2. Check with the manufacturer block/regional patibility criteria. 畢業(yè)設(shè)計(jì)（論文）專用紙 第 頁 20 3. Consider using the second spreadsheets formulate FPGA layout to determine what tube feet is a universal, which is dedicated, which support difference signal to the and global and local clock, which need reference voltage. 4. Utilizing the above two spreadsheets information and regional patibility criterion, first distribution restricted the biggest signal to the extent the last distribution on pins, the smallest restricted. For example, you may need to distribution serial bus and the clock signal, because they usually only assigned to some special. At this stage, considering writing a contains only port distribution of HDL files. Then through the use of suppliers of tools or using a text editor manually create a limit files, for I/O standards and increase the SSO necessary support information. Ready for