【正文】 The designer is aware of how data flows between hardware registers and how the data is processed in the design. Gate level The module is implemented in terms of logic gates and interconnections between these gates. Design at this level is similar to describing a design in terms of a gatelevel logic diagram. Switch level This is the lowest level of abstraction provided by Verilog. A module can be implemented in terms of switches, storage nodes, and the interconnections between them. Design at this level requires knowledge of switchlevel implementation details. Four levels of abstraction levels of abstraction (why) Verilog allows the designer to mix and match all four levels of abstractions in a design ? In the digital design munity, the term register transfer level (RTL) is frequently used for a Verilog description that uses a bination of behavioral and dataflow constructs and is acceptable to logic synthesis tools. ? If a design contains four modules, Verilog allows each of the modules to be written at a different level of abstraction. ? As the design matures, most modules are replaced with gatelevel implementations. Normally, the higher the level of abstraction, the more flexible and technologyindependent the design. ? As one goes lower toward switchlevel design, the design bees technologydependent and inflexible. ? A small modification can cause a significant number of changes in the design. ? Consider the analogy with C programming and assembly language programming. It is easier to program in a higherlevel language such as C. The program can be easily ported to any machine. However, if you design at the assembly level, the program is specific for that machine and cannot be easily ported to another machine. Instances A module provides a template from which you can create actual objects. When a module is invoked, Verilog creates a unique object from the template. Each object has its own name, variables, parameters, and I/O interface. The process of creating objects from a module template is called instantiation, and the objects are called instances. In Example 21, the toplevel block creates four instances from the Tflipflop (T_FF) template. Each T_FF instantiates a D_FF and an inverter gate. Each instance must be given a unique name. Example 21 Module Instantiation module ripple_carry_counter(q, clk, reset)。 output q。 module T_FF(q, clock, reset)。 endmodule ? In the above module, four instances of the module T_FF (Tflipflop) are used. Therefore, we must now define the internals of the module T_FF module T_FF(q, clk, reset)。 input d, clk, reset。 reg reset。 15 reset = 139。 endmodule Once the stimulus block is pleted, we are ready to run the simulation and verify the functional correctness of the design block. The output obtained when stimulus and design blocks are simulated is shown 0 Output q = 0 20 Output q = 1 30 Output q = 2 40 Output q = 3 50 Output q = 4 60 Output q = 5 70 Output q = 6 80 Output q = 7 90 Output q = 8 100 Output q = 9 110 Output q = 10 120 Output q = 11 130 Output q = 12 140 Output q = 13 150 Output q = 14 160 Output q = 15 170 Output q = 0 180 Output q = 1 190 Output q = 2 195 Output q = 0 210 Output q = 1 220 Output q = 2 Summary In this chapter we discussed the following concepts. ? Two kinds of design methodologies are used for digital design: topdown and bottomup. A bination of these two methodologies is used in today39。 180 reset = 139。 ripple_carry_counter r1(q, clk, reset)。 // Lots of new constructs. Ignore the functionality of the // constructs. // Concentrate on how the design block is built in a topdown fashion. always (posedge reset or negedge clk) if (reset) q = 139。 input clk, reset。 output [3:0] q。 wire d。 //I/O signals and vector declarations input clk, reset。 5) 布局布線 ： 把用 綜合器自動生成的門級網(wǎng)表（ EDIF）通過運行一個自動操作的布局布線工具，使其與具體的某種 FPGA或某種 ASIC工藝庫器件對應(yīng)起來，并加以連接的過程。 bin = bin +5。 reg [7:0] ain, bin。 always (posedge clock or negedge reset) if (!reset) begin a_reg = ‘b0。 output out。 always (sl or a or b) if (!sl) out = a。 行為級：技術(shù)指標和算法的 Verilog描述 RTL級：邏輯功能的 Verilog描述 門級 ：邏輯結(jié)構(gòu)的 Verilog描述 開關(guān)級：具體的晶體管物理器件的描述