現(xiàn)代cmos工藝基本流程課件(ppt79頁)-文庫吧在線文庫
【正文】 Metal1 IMD1 W Via Plug 鎢和 TiN拋光 ? 鎢和 TiN拋光 –同第一層互連 70 Trench Oxide Polysilicon Cross Section N Well P Well N+ Source/Drain P+ Source/Drain Spacer Contact Metal1 Via1 平面視圖 通孔 ? 完成通孔 71 Silicon Substrate P+ Silicon Epi Layer P P Well N Well N+ Drain N+ Source P+ Drain P+ Source BPSG W Contact Plug Metal1 IMD1 W Via Plug Metal2 Metal2淀積 ? Metal2淀積 –類似于 Metal1 –厚度和寬度增加，連接更長的距離，承載更大的電流 72 Silicon Substrate P+ Silicon Epi Layer P P Well N Well N+ Drain N+ Source P+ Drain P+ Source BPSG W Contact Plug Metal1 Photoresist IMD1 W Via Plug Metal2 光刻膠成形 ? 光刻膠成形 –相鄰的金屬層連線方向垂直，減小層間的感應(yīng)耦合 73 Silicon Substrate P+ Silicon Epi Layer P P Well N Well N+ Drain N+ Source P+ Drain P+ Source BPSG W Contact Plug Metal1 Photoresist IMD1 W Via Plug Metal2 Metal2刻蝕 ? Metal2刻蝕 –類似于 Metal1 74 Silicon Substrate P+ Silicon Epi Layer P P Well N Well N+ Drain N+ Source P+ Drain P+ Source BPSG W Contact Plug Metal1 IMD1 W Via Plug Metal2 除去光刻膠 75 Trench Oxide Polysilicon Cross Section N Well P Well N+ Source/Drain P+ Source/Drain Spacer Contact Metal1 Via1 Metal2 平面視圖 第二層互連 ? 完成第二層互連，后面的剖面圖將包括右上角的壓焊點 76 Silicon Substrate P+ Silicon Epi Layer P P Well N Well N+ Drain N+ Source P+ Drain P+ Source BPSG W Contact Plug Metal1 IMD1 W Via Plug Passivation Metal2 鈍化層淀積 ? 鈍化層淀積 –多種可選的鈍化層， Si3N SiO2和聚酰亞胺等 –保護電路免受刮擦、污染和受潮等 77 Silicon Substrate P+ Silicon Epi Layer P P Well N Well N+ Drain N+ Source P+ Drain P+ Source BPSG W Contact Plug Metal1 IMD1 W Via Plug Passivation Bond Pad Poly Gate Gate Oxide Silicide Spacer Metal2 鈍化層成形 ? 鈍化層成形 –壓焊點打開，提供外界對芯片的電接觸 78 Cross Section Trench Oxide N+ Source/Drain P+ Source/Drain Spacer Contact Metal1 Polysilicon Via1 +5V Supply VOUT N Well P Well Metal2 Ground Bond Pad VIN 平面視圖 完成 ? 完成，顯示了電氣連接和部分壓焊點 79 完成 演講完畢，謝謝觀看！ 。CMOS工藝 1 CMOS，全稱 Complementary Metal Oxide Semiconductor，即互補金屬氧化物半導(dǎo)體，是一種大規(guī)模應(yīng)用于集成電路芯片制造的原料。) main conductor TiN (500197。1197。) –用作晶體管的柵絕緣層 24 Silicon Substrate P+ Silicon Epi Layer P P Well N Well Polysilicon 多晶硅淀積 ? 多晶硅淀積 –厚度 150~300nm –化學(xué)氣相淀積 (CVD) 25 Silicon Substrate P+ Silicon Epi Layer P P Well N Well Photoresist Channel Length Polysilicon 光刻膠成形 ? 光刻膠成形 –工藝中最關(guān)鍵的圖形轉(zhuǎn)移步驟 –柵長的精確性是晶體管開關(guān)速度的首要決定因素 –使用最先進(jìn)的曝光技術(shù) ——深紫外光 (DUV) –光刻膠厚度比其他步驟薄 26 Silicon Substrate P+ Silicon Epi Layer P P Well N Well Photoresist Channel Length 多晶硅刻蝕 ? 多晶硅刻蝕 –基于氟的反
教學(xué)課件相關(guān)推薦
鄂ICP備17016276號-1