【正文】 采用 CMOS技術(shù)可以將成對的金屬氧化物半導(dǎo)體場效應(yīng)晶體管（MOSFET）集成在一塊硅片上。) –用作晶體管的柵絕緣層 24 Silicon Substrate P+ Silicon Epi Layer P P Well N Well Polysilicon 多晶硅淀積 ? 多晶硅淀積 –厚度 150~300nm –化學(xué)氣相淀積 (CVD) 25 Silicon Substrate P+ Silicon Epi Layer P P Well N Well Photoresist Channel Length Polysilicon 光刻膠成形 ? 光刻膠成形 –工藝中最關(guān)鍵的圖形轉(zhuǎn)移步驟 –柵長的精確性是晶體管開關(guān)速度的首要決定因素 –使用最先進的曝光技術(shù) ——深紫外光 (DUV) –光刻膠厚度比其他步驟薄 26 Silicon Substrate P+ Silicon Epi Layer P P Well N Well Photoresist Channel Length 多晶硅刻蝕 ? 多晶硅刻蝕 –基于氟的反應(yīng)離子刻蝕 (RIE) –必須精確的從光刻膠得到多晶硅的形狀 27 Silicon Substrate P+ Silicon Epi Layer P P Well N Well Gate Oxide Poly Gate Electrode 除去光刻膠 28 Trench Oxide N Well P Well Cross Section Polysilicon 平面視圖 柵極 ? 完成柵極 29 Silicon Substrate P+ Silicon Epi Layer P P Well N Well Gate Oxide Poly Gate Electrode Poly Reoxidation 多晶硅氧化 ? 多晶硅氧化 –在多晶硅表面生長薄氧化層 –用于緩沖隔離多晶硅和后續(xù)步驟形成的Si3N4 30 Silicon Substrate P+ Silicon Epi Layer P P Well N Well Photoresist 光刻膠成形 ? 光刻膠成形 –用于控制 NMOS管的銜接注入 31 Silicon Substrate P+ Silicon Epi Layer P P Well N Well Photoresist Arsenic () Ions N Tip NMOS管銜接注入 ? NMOS管銜接注入 –低能量、淺深度、低摻雜的砷離子注入 –銜接注入用于削弱柵區(qū)的熱載流子效應(yīng) 32 Silicon Substrate P+ Silicon Epi Layer P P Well N Well N Tip 除去光刻膠 33 Silicon Substrate P+ Silicon Epi Layer P P Well N Well Photoresist N Tip 光刻膠成形 ? 光刻膠成形 –用于控制 PMOS管的銜接注入 34 Silicon Substrate P+ Silicon Epi Layer P P Well N Well Photoresist BF2 (+) Ions N Tip P Tip ? PMOS管銜接注入 –低能量、淺深度、低摻雜的 BF2+離子注入 –銜接注入用于削弱柵區(qū)的熱載流子效應(yīng) PMOS管銜接注入 35 Silicon Substrate P+ Silicon Epi Layer P P Well N Well N Tip P Tip 除去光刻膠 36 Silicon Substrate P+ Silicon Epi Layer P P Well N Well Silicon Nitride Thinner Here Thicker Here N Tip P Tip P Tip Si3N4淀積 ? Si3N4淀積 –厚度 120～ 180nm – CVD 37 Silicon Substrate P+ Silicon Epi Layer P P Well N Well Spacer Sidewall N Tip P Tip P Tip Si3N4刻蝕 ? Si3N4刻蝕 –水平表面的薄層 Si3N4被刻蝕，留下隔離側(cè)墻 –側(cè)墻精確定位晶體管源區(qū)和漏區(qū)的離子注入 – RIE 38 Silicon Substrate P+ Silicon Epi Layer P P Well N Well Photoresist N Tip P Tip 光刻膠成形 ? 光刻膠成形 –用于控制 NMOS管的源 /漏區(qū)注入 39 Silicon Substrate P+ Silicon Epi Layer P P Well N Well Photoresist Arsenic () Ions N+ Drain N+ Source P Tip NMOS管源 /漏注入 ? NMOS管源 /漏注入 –淺深度、重摻雜的砷離子注入，形成了重摻雜的源 /漏區(qū) –隔離側(cè)墻阻擋了柵區(qū)附近的注入 40 Silicon Substrate P+ Silicon Epi Layer P P Well N Well N+ Drain N+ Source P Tip 除去光刻膠 41 Silicon Substrate P+ Silicon Epi Layer P P Well N Well N+ Drain N+ Source Photoresist P