【正文】 17]。 圖 是 8 位分段電容逐次逼近 ADC 模擬部分的結(jié)構(gòu)圖，分段電容 Cs 將兩個(gè)獨(dú)立的二進(jìn)制加權(quán)電容陣列分隔（當(dāng)分段電容兩邊二進(jìn)制加權(quán)電容陣列位數(shù)相等時(shí)，整個(gè)逐次逼近 ADC 的總電容最?。?，低 4 位二進(jìn)制加權(quán)電容陣列還有一個(gè)與 LSB 電容等值的 Cc。如果 比較器輸出 1， 還需要將開(kāi)關(guān) S1接 回到 地。 電荷定標(biāo)型逐次逼近 ADC 電荷定標(biāo) 型逐次逼近 ADC 是目前應(yīng)用較 多 的一種類型，它 利 用電容 通過(guò) 電荷再分配 完成二進(jìn)制搜索算法 ，因此功耗一般比較小，而且不需要額外的采樣保持電路。 使用二進(jìn)制加權(quán)電流源陣列的 逐次逼近 ADC 如圖 所示 [8]，它使用 等效寬長(zhǎng)比為二進(jìn)制加權(quán)的 MOS 管組成的二進(jìn)制加權(quán)的電流源陣列，可以通過(guò)電流比較器將輸入電壓轉(zhuǎn)換成電流，然后與這些電流源的組合電流進(jìn)行比較，也可以將這些電流源的 組合電流轉(zhuǎn)換成相應(yīng)電壓，然后與輸入電壓通過(guò)電壓比較器進(jìn)行比較。按照 逐次逼近 ADC 結(jié)構(gòu)中 DAC 的工作原理，大致可以將 逐次逼近ADC 分 成 三種：電壓定標(biāo)、電流定標(biāo)、電荷定標(biāo)， 下面分別予以討論。這樣， 逐次逼近 ADC 的最高位就確定了，下面再確定次高位，即先預(yù)置 SAR 次高位為 1，如果前一個(gè)轉(zhuǎn)換周期確定的 MSB = 1，那么此時(shí) DAC 輸出 3/4 Vref， Vin 與 3/4 Vref比較大小，從而確定 SAR 次高位；如果前一個(gè)轉(zhuǎn)換周期確定的 MSB = 0，那么此時(shí) DAC 輸出 1/4 Vref， Vin 與 1/4 Vref比較大小，從而確定 SAR 次高位。 模擬部分版圖與數(shù)字部分版圖的拼接，整體版圖的設(shè)計(jì)，流片。而在電機(jī)控制應(yīng)用中，需要在同一時(shí)刻及時(shí)捕獲多路模擬輸入，完成三相電流和電壓測(cè)量，這樣在一個(gè)芯片 上 集成多個(gè) 采樣 /保持電路 的逐次逼近 ADC 就為這類應(yīng)用提供了極大的便利。 關(guān)鍵詞： 逐次逼近 模數(shù)轉(zhuǎn)換器 數(shù)模轉(zhuǎn)換器 比較器 Abstract II Abstract Successive approximation analogtodigital converters (ADCs) have medium resolution and medium speed, small chip area and low power consumption can also be achieved in CMOS process. Moreover, it is convenient to make multichannel conversion. Due to their mixed advantages in resolution, speed, power and cost, successive approximation ADCs are widely applied in industry controlling, medical instruments, auxiliary analogtodigital interfaces of microprocessors and so on. A , 12bit, 500kS/s lowpower successive approximation ADC is designed in this thesis, which adopts single railtorail input and has powerdown mode. Study work can be categorized into 3 parts: ① A segmented capacitive digitalto analog converter (DAC) is designed with 2 separated 6bit arrays which consist of 128 unit capacitors in all, resulting in smaller chip area and lower dynamic power. Moreover, thermometer coding is applied to the top 3 bits, ensuring the DAC’s monotonicity. Common centroid geometry is introduced in the layout to improve matching property. ② A multistage parator is designed, which is posed of 3 preamplifiers and a latch. Each preamplifier is optimized according to its position, the design of them and the analog buffer has already taken kickback noise into consideration. An offset cancellation technique is applied too. Simulation results show that, the proposed parator can distinguish input with 10mV offset at 10MHz, while its power is 600uW. ③ The control circuit is designed in several modules, which is described in verilogHDL, synthesized, placed and routed automatically. This digital block coordinates analog circuits to finish the successive approximation, and switches the chip into powerdown mode or work mode. After circuit design and simulation, the physical layout design, postsimulation and chip measurement are also finished. The proposed ADC is designed and fabricated in UMC Mixed Mode CMOS process, occupying 1mm. Measurement results show that, its SNDR achieves at 500kS/s, thus ENOB is , and |DNL| is less than 2LSB, |INL| is less than 4LSB, with overall power only . Keywords: successive approximation ADC DAC parator 目 錄 III 目 錄 第 1 章 引言 ...............................................................................................................1 選題背景及意義 ...............................................................................................1 研究工作主要內(nèi)容 ...........................................................................................2 論文各部分主要內(nèi)容 .......................................................................................3 第 2 章 逐次逼近 ADC 概述 .....................................................................................4 逐次逼近 ADC 的工作原理 .............................................................................4 逐次逼近 ADC 的典型結(jié)構(gòu) .............................................................................5 電壓定標(biāo)型逐次逼近 ADC ........................................................................5 電流定標(biāo)型逐次逼近 ADC ........................................................................7 電荷定標(biāo)型逐次逼近 ADC ........................................................................8 其他結(jié)構(gòu)逐次逼近 ADC ..........................................................................13 逐次逼近 ADC 的研究現(xiàn)狀 ...........................................................................13 第 3 章 DAC 的研究與設(shè)計(jì) ....................................................................................15 DAC 結(jié)構(gòu)的選擇 ............................................................................................15 分段電容 DAC 的工作原理 ...........................................................................15 分段電容 DAC 的電路設(shè)計(jì) ...........................................................................17 分段電 容 DAC 的版圖設(shè)計(jì) ...........................................................................22 電容匹配精度 ...........................................................................................22 抑制干擾 ...................................................................................................25 第 4 章 比較器的研究與設(shè)計(jì) .................................................................................25 比較器的典型結(jié)構(gòu) .........................................................................................25 運(yùn)放結(jié)構(gòu)比較器 .......................................................................................25 Latch 比較器 .............................................................................................26 高速高精度比較器 ...................................................................................29 比較器的失調(diào)校準(zhǔn) .........................................................................................30 比較器的設(shè)計(jì) .................................................................................................32 比較器結(jié)構(gòu)的選擇 ...................................................................................32 第一級(jí)運(yùn)放的設(shè)計(jì) .....