【正文】 to a corresponding value of analog voltage or current. To generate a fixedfrequency sine wave, a constant value (the phase increment—which is determined by the binary number) is added to the phase accumulator with each clock cycle. If the phase increment is large, the phase accumulator will step quickly through the sine lookup table and thus generate a high frequency sine wave. If the phase increment is small, the phase accumulator will take many more steps, accordingly generating a slower waveform. 2 Analog Dialogue 3808, August (2020)What do you mean by a plete DDS? The integration of a D/A converter and a DDS onto a single chip is monly known as a plete DDS solution, a property mon to all DDS devices from ADI. Let’s talk some more about the phase accumulator. How does it work? Continuoustime sinusoidal signals have a repetitive angular phase range of 0 to 2. The digital implementation is no different. The counter’s carry function allows the phase accumulator to act as a phase wheel in the DDS implementation.To understand this basic function, visualize the sinewave oscillation as a vector rotating around a phase circle (see Figure 4). Each designated point on the phase wheel corresponds to the equivalent point on a cycle of a sine wave. As the vector rotates around the wheel, visualize that the sine of the angle generates a corresponding output sine wave. One revolution of the vector around the phase wheel, at a constant speed, results in one plete cycle of the output sine wave. The phase accumulator provides the equally spaced angular values acpanying the vector’s linear rotation around the phase wheel. The contents of the phase accumulator correspond to the points on the cycle of the output sine wave.n812162024283248NUMBER OF POINTS2564096655351048576167772162684354564294967296281474976710656M0000...01111...1fO=M  fC2NJUMP SIZEFigure 4. Digital phase wheel. The phase accumulator is actually a moduloM counter that increments its stored number each time it receives a clock pulse. The magnitude of the increment is determined by the binarycoded input word (M). This word forms the phase step size between referenceclock updates。 each phase shift can represent two signal elements. The AD9830, AD9831, AD9832, and AD9835 provide four phase registers to allow plex phase modulation schemes to be implemented by continuously updating different phase offsets to the registers. Can multiple DDS devices be synchronized for, say, IQ capability?It is possible to use two single DDS devices that operate on the same master clock to output two signals whose phase relationship can then be directly controlled. In Figure 8, two AD9834s are programmed using one reference clock, with the same reset pin being used to update both parts. Using this setup, it is possible to do IQ modulation.MCLKRESETAD9834AD9834PHASESHIFTFigure 8. Multiple DDS ICs in synchronous mode.4 Analog Dialogue 3808, August (2020)A reset must be asserted after powerup and prior to transferring any data to the DDS. This sets the DDS output to a known phase, which serves as the mon reference point that allows synchronization of multiple DDS devices. When new data is sent simultaneously to multiple DDS units, a coherent phase relationship can be maintained, and their relative phase offset can be predictably shifted by means of the phaseoffset register. The AD9833 and AD9834 have 12 bits of phase resolution, with an effective resolution of degree. [For further details on synchronizing multiple DDS units please see Application Note AN605.] What are the key performance specs of a DDS based system?Phase noise, jitter, and spuriousfree dynamic range (SFDR). Phase noise is a measure (dBc/Hz) of the shortterm frequency instability of the oscillator. It is measured as the singlesideband noise resulting from changes in frequency (in decibels below the amplitude at the operating frequency of the oscillator using a 1Hz bandwidth) at two or more frequency displacements from the operating frequency of the oscillator. This measurement has particular application to performance in the analog munications industry.Do DDS devices have good phase noise?Noise in a sampled system depends on many factors. Referenceclock jitter can be seen as phase noise on the fundamental signal in a DDS sy