【正文】 (b) fOUT = MHz. Figure 12. Typical display of programming sequence.How can I evaluate your DDS devices?All DDS devices have an evaluation board available for purchase. They e with dedicated software, allowing the user to test/evaluate the part easily within minutes of receiving the board. A technical note acpanying each evaluation board contains schematic information and shows best remended boarddesign and layout practice.Where can I find more information on DDS devices?The main DDS homepage is located at Links to design tools are provided at Analog_Root/static/techSupport/interactiveTools/ddsAn indepth tutorial on DDS technology can be found at AN605 can be found at UploadedFiles/Application_Notes/371092853519044414816The latest DDS selection guide can be found at 。 and phase truncation may introduce an error level into the system, depending on the code word chosen. For a ratio that can be exactly expressed by a truncated binarycoded word, there is no truncation error. For ratios requiring more bits than are available, the resulting phase noise truncation error results in spurs in a spectral plot. Their magnitudes and distribution depends on the code word chosen. The DAC also contributes to noise in the system. DAC quantization or linearity errors will result in both noise and harmonics. Figure 9 shows a phase noise plot for a typical DDS device—in this case an AD9834.FREQUENCY (Hz)dBc/Hz–100–110–120–130–140–150–160100 1k 10k 100k 200kAVDD= DVDD= 3VTA= 25CFigure 9. Typical output phase noise plot for the AD9834. Output frequency is 2 MHz and M clock is 50 MHz.What about jitter?Jitter is the dynamic displacement of digital signal edges from their longterm average positions, measured in degrees rms. A perfect oscillator would have rising and falling edges occurring at precisely regular moments in time and would never vary. This, of course, is impossible, as even the best oscillators are constructed from real ponents with sources of noise and other imperfections. A highquality, lowphasenoise crystal oscillator will have jitter of less than 35 picoseconds (ps) of period jitter, accumulated over many millions of clock edgesJitter in oscillators is caused by thermal noise, instabilities in the oscillator electronics, external interference through the power rails, ground, and even the output connections. Other influences include external magic or electric fields, such as RF interference from nearby transmitters, which can contribute jitter affecting the oscillator’s output. Even a simple amplifier, inverter, or buffer will contribute jitter to a signal.Thus the output of a DDS device will add a certain amount of jitter. Since every clock will already have an intrinsic level of jitter, choosing an oscillator with low jitter is critical to begin with. Dividing down the frequency of a highfrequency clock is one way to reduce jitter. With frequency division, the same amount of jitter occurs within a longer period, reducing its percentage of system time. In general, to reduce essential sources of jitter and avoid introducing additional sources, one should use a stable reference clock, avoid using signals and circuits that slew slowly, and use the highest feasible reference frequency to allow increased oversampling. SpuriousFree Dynamic Range (SFDR) refers to the ratio (measured in decibels) between the highest level of the fundamental signal and the highest level of any spurious, signal—including aliases and harmonically related frequency ponents—in the spectrum. For the very best SFDR, it is essential to begin with a highquality oscillator. SFDR is an important specification in an application where the frequency spectrum is being shared with other munication channels and applications. If a transmitter’s output sends spurious signals into other frequency bands, they can corrupt, or interrupt neighboring signals. Typical output plots taken from an AD9834 (10bit DDS) with a 50MHz master clock are shown in Figure 10. In (a), the output frequency is exactly 1/3 of the master clock frequency (MCLK). Because of the judicious choice of frequencies, there are no harmonic frequencies in the 25MHz window, aliases are minimized, and the spurious behavior appears excellent, with all spurs at least 80 dB below the signal (SFDR = 80 dB). The lower frequency setting in (b) has more points to shape the waveform (but not enough for a really clean waveform), and gives a more realistic picture。 phasecontinuous frequency hops with no overshoot/undershoot or analogrelated loop settlingtime anomalies, ? the digital architecture of