【導讀】{ "log_id": 4485646962645810853, "error_code": 282002, "error_msg": "input encoding error" }

　　

【正文】 cillator electronics, external interference through the power rails, ground, and even the output connections. Other influences include external magic or electric fields, such as RF interference from nearby transmitters, which can contribute jitter affecting the oscillator’s output. Even a simple amplifier, inverter, or buffer will contribute jitter to a signal.Thus the output of a DDS device will add a certain amount of jitter. Since every clock will already have an intrinsic level of jitter, choosing an oscillator with low jitter is critical to begin with. Dividing down the frequency of a highfrequency clock is one way to reduce jitter. With frequency division, the same amount of jitter occurs within a longer period, reducing its percentage of system time. In general, to reduce essential sources of jitter and avoid introducing additional sources, one should use a stable reference clock, avoid using signals and circuits that slew slowly, and use the highest feasible reference frequency to allow increased oversampling. SpuriousFree Dynamic Range (SFDR) refers to the ratio (measured in decibels) between the highest level of the fundamental signal and the highest level of any spurious, signal—including aliases and harmonically related frequency ponents—in the spectrum. For the very best SFDR, it is essential to begin with a highquality oscillator. SFDR is an important specification in an application where the frequency spectrum is being shared with other munication channels and applications. If a transmitter’s output sends spurious signals into other frequency bands, they can corrupt, or interrupt neighboring signals. Typical output plots taken from an AD9834 (10bit DDS) with a 50MHz master clock are shown in Figure 10. In (a), the output frequency is exactly 1/3 of the master clock frequency (MCLK). Because of the judicious choice of frequencies, there are no harmonic frequencies in the 25MHz window, aliases are minimized, and the spurious behavior appears excellent, with all spurs at least 80 dB below the signal (SFDR = 80 dB). The lower frequency setting in (b) has more points to shape the waveform (but not enough for a really clean waveform), and gives a more realistic picture。 the largest spur, at the secondharmonic frequency, is about 50 dB below the signal (SFDR = 50 dB).Analog Dialogue 3808, August (2020) 5Do you have tools that make it easier to program and predict the performance of the DDS?The online interactive design tool is an assistant for selecting tuning words, given a reference clock and desired output frequencies and/or phases. The required frequency is chosen, and idealized output harmonics are shown after an external reconstruction filter has been applied. An example is shown in Figure 11. Tabular data is also provided for the major images and harmonics. Figure 11. Screen presentation provided by an interactive design tool. A sinx/x presentation of a typical device output.How will these tools help me program the DDS?All that’s needed is the required frequency output and the system’s reference clock frequency. The design tool will output the full programming sequence required to program the part. In the example in Figure 12, the MCLK is set to 25 MHz and the desired output frequency is set to 10 MHz. Once the update button is pressed, the full programming sequence to program the part is contained in the Init Sequence register. dB0–10–20–30–40–50–60–70–80–90–1600 25MRWB 1K ST200 SECVWB 300FREQUENCY (Hz)dB0–10–20–30–40–50–60–70–80–90–1600 25MRWB 1K ST200 SECVWB 300FREQUENCY (Hz)(a) (b)Figure 10. Output of an AD9834 with a 50MHz master clock and (a) fOUT = MHz (., MCLK/3)。 (b) fOUT = MHz. Figure 12. Typical display of programming sequence.How can I evaluate your DDS devices?All DDS devices have an evaluation board available for purchase. They e with dedicated software, allowing the user to test/evaluate the part easily within minutes of receiving the board. A technical note acpanying each evaluation board contains schematic information and shows best remended boarddesign and layout practice.Where can I find more information on DDS devices?The main DDS homepage is located at Links to design tools are provided at Analog_Root/static/techSupport/interactiveTools/ddsAn indepth tutorial on DDS technology can be found at AN605 can be found at UploadedFiles/Application_Notes/371092853519044414816The latest DDS selection guide can be found at