eda課程設(shè)計(jì)報(bào)告n溝道m(xù)os管工藝模擬與器件模擬(文件)
【正文】 氧化對(duì)擴(kuò)散工藝的影響 附錄： 實(shí) 驗(yàn)程序 go athena 定義網(wǎng)格 X line x loc= spac= line x loc= spac= line x loc= spac= line x loc= spac= 定義網(wǎng)格 Y line y loc= spac= line y loc= spac= line y loc= spac= line y loc= spac= InitialSiliconStructurewith100Orientation初始硅的 100晶向 ,P型襯底 init silicon =4e14 orientation=100 =2 structure outfile= GateOxidation柵氧化 diffus time=12 temp=910 dryo2 press= =3 structure outfile= Extract a design parameter抽取設(shè)計(jì)參數(shù) extract name=gateox thickness oxide =1 = vt adjust implant 閾值電壓調(diào)整注入 implant boron dose=2e12 energy=10 pearson structure outfile= depo poly thick= divi=10 structure outfile= 柵刻蝕 etch poly left = structure outfile= 多晶硅氧化 method fermi press diffuse time=3 temp=920 weto2 press= structure outfile= 多晶摻雜 implant phosphor dose= energy=15 pearson structure outfile= depo oxide thick= divisions=8 structure outfile= etch oxide dry thick= structure outfile= implant arsenic dose= energy=30 pearson structure outfile= method fermi press diffuse time=1 temp=900 nitro press= structure outfile= pattern s/d contact metal etch oxide left = deposit alumin thick= divi=2 etch alumin right = structure outfile= Extract design parameters extract final S/D Xj extract name=nxj xj silicon =1 = =1 extract the N++ regions sheet resistance extract name=n++ sheet rho material=Silicon =1 = =1 extract the long chan Vt extract name=n1dvt 1dvt ntype vb= qss=1e10 = extract the surface conc under the channel. extract name=chan surf conc impurity=Net Doping \ material=Silicon =1 = structure mirror right electrode name=gate x= electrode name=source x= electrode name=drain x= electrode name=substrate backside structure outfile= tonyplot yaojinpeng_nmos*.str go atlas mesh infile= set material models models cvt srh print contact name=gate interface qf=2e10 method gummel newton solve init solve vgate= outfile=solve_tmp1 solve vgate= outfile=solve_tmp2 solve vgate= outfile=solve_tmp3 solve vgate= outfile=
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