【正文】 the numerical precision. Larger word sizes are possible if the number of MAC units per chips is reduced. The increase in density of FPGAs in the future will certainly expand the design space available to the designer, and make such constraints less severe.. Implementation of MultiplierThe binatorial multiplier uses one CLB per partial product bit.A 2inputAND gate generates each partial product, but additional circuitry is required to add together all partial products of equal weight. The total number of CLBs used for the multiplier in this case is 64 and the basic cell structure is illustrated in Figure 2.Each cell is configured as a full adder (except for the type A cell). This full adder accepts a sum and a carry from a previous operation of equal weight, as shown in Figure 2, and the logical AND of the inputs xi and ai.The sum and carry generated by the adder are then sent to the CLBs of proper weight as shown in Figure 3. The multiplier has been configured to perform multiplication of signed numbers in two’s plement notation. The small circles in the figure indicate negative inputs or outputs。 the dashed linedenotes the diagonal of the carrysave section. As the 4 least significant bits are discarded, the delay elements shown in the dotted squares need not be implemented. After the required number of multiplications and accumulations are made, the output should be clocked out and the accumulator reset. The structure of FIR filters facilitates their implementation using the pipelined MAC unit. The filter coefficients and the corresponding delayed inputs are fed to the multiplier in synchronized data streams, with their arrivals corresponding to the basic clock rate. An N tap filter requires N+1 clock cycles to plete the putation of one output.. FPGA ImplementationUnlike the unpipelined MAC unit, the routing delay is very critical in the pipelined MAC. This is because it takes ns for the output of the pipeline register to stabilize after it gets the clock, the output is then routed, and finally there is a ns delay in the next CLB Thus there is a minimum delay of ns and unless proper care is exercised, the routing delays may dominat。 these columns are represented in the layout by the small circles at the inputs to the adders. The numerous shifts encountered in the shift and add approach will very easily exhaust the routing resources. We have provided an empty column between every stage, which frees up additional routing resources. As shown in Figure 10, one second order section is placed on top of the other, for reasons discussed above, though the 24 columns available in the XC4013 might seem to satisfy the requirements for the two sections, which total only 23columns. The adders in this implementation use 22 bits, and the most significant 14 bits of the output of the dedicated carry adders are fed to the shift and add blocks.The sampling rate achieved with this configuration was morethan 10MHz.A number of other example fixedpoint filters were designed to evaluate the utility of this approach。 重慶大學(xué)本科學(xué)生畢業(yè)設(shè)計(jì)（論文）附件 附件D：FPGA IMPLEMENTATION OF DIGITAL FILTERSChiJui Chou, Satish Mohanakrishnan, Joseph B. EvansTelemunicationsamp。 such bits have to be subtracted rather than being added. The cells in the leftmost column of the array only AND their two inputs and generate the product. If one of the two inputs has a negative weight, then the output will have a negative weight. The conventional 1bit full adder assumes positive weights on all of its 3 inputs and 2 an adder can be generalized to four types of adder cells by attaching positive and negative weights to the input/output pins as discussed in [7]. Figure 4 lists the logic symbols for the fourtypes of generalized full adders.The Boolean equations governing the Type 0 and 3 full adders areand those for the Type 1 and 2 adders areType 0 and Type 3 full adders are characterized by the same pair of logic equations, identical to that of the conventional 1bit full adder (Type 0). This is becausea Type 3 full adder can be obtained from a Type 0 full adder by negating all of the input and output values and vice versa. A similar relationship can be established between Type 1 and Type 2 full adders. For Type 0, 1, 2, and 3 full adders, the two independent 4bit functions were used to generate the sum and carry outputs. We can easily include the AND gate in the CLB just by replacing, for example, X with(xi and ai) when configuring the CLB. The horizontal inputs(xi,ai) can use the horizontal longlines which are associated with each row for distribution of the signal with a very short routing delay. Other interconnections can be made using the singlelength or doublelength lines via ProgrammableInterconnection Points (PIP) or switching matrices.. Adder ImplementationIn the XC4000 series, each CLB includes highspeed carry logic that can be activated by configuration. The two 4input functionGenerators may be configured as a 2bit adder with builtin hidden carry that can be expanded to any length. The 16bit adder in our MAC unit, which uses the dedicated carry logic, requires nine CLBs. The middle 14bits use 7 CLBs, one CLB is used for the MSB, and one is used for the LSB of the adder. For each CLB in the middle section, the F function is used for lowerorder bit and the G function is used for higherorder bit. Obviously, we need to use the G function for the LSB bit and F function for the MSB bit. In the case of the LSB CLB, two values must be input on the G1 and G4 pins. The carry signal enters on the F1 pin,propagates through the G carry logic, and exits on the COUT pin. The F function of this CLB is not used and can be used for other purposes. For the middle CLBs, the logic is configured to perform a 2bit addition of A+B in both the F and G functions,with the lowerorder A and B inputs on the F1 and F2 p