【正文】 ins, andthe higherorder A and B inputs on the G1 and G4 pins. The carry signal enters on the CIN pin, propagates through the F and G carry logic, and exits on the COUT pin. For the MSB CLB, the two values must be input on F1 and F2 pins. The carry signal enters on the CIN pin, propagates through the F carry logic, and exits on the COUT pin. The G function generator of this CLB is used to access the carry out signal or calculate a two’s plement overflow.The limitation of using this builtin carry logic is that the carry out (COUT) pin of a CLB can only be connected to the carry in (CIN) pin of the CLBs above or below. Thus the adder using fast carry logic can only be configured vertically in the array.The dedicated carry circuitry greatly increases the efficiency and performance of adders. Conventionalmethods for improving performance such as carry generate/propagate are not useful even at 16bit level, and are of marginal benefit at longer our case, the 16bit adder has a binatorial delay of only ns.. MAC ImplementationWe use the most significant 8 output bits of the multiplier as the input to the low order bits of the adder. The 8bit input of the adder is signextended and added with previous outputs using two’s plement addition.The basic structure of the MAC unit can use pipeline registersbetween the multiplier and accumulator to increase the flipflops in the CLBs are used as pipeline registers and hence noadditional CLBs are needed.The layout of a single MAC unit on an XC4000series part isshown in Figure 5.The performance of the MAC unit with an 8bit by 8bit multiply and 16 bit accumulator is determined by the speed of the multiplier. The worst case multiplier delay reported is approaching 100 ns. The MAC unit can thus support a clock speed better than 10 MHz. With the use of the horizontal longlines to distribute the critical path signals, the speed can be further improved,although this may restrict the use of the MAC unit in various system configurations. The implementation of a MAC unit on an XC4000series part requires 73 CLBs. FILTERS. Filter StructuresThe transfer function of an N tap FIR filter is given by This structure can be realized in many ways, such as the canonical form, pipelined form, and inverted form as depicted in Figure 6. . High Performance Filters on FPGAsThe inverted form shown in Figure 6(c) is wellsuited for achieving a high sampling rate even for higher order filters. This is possible because the throughput does not depend strongly on the number of taps due to extensive pipelining. The fact that the multipliers occupy a large area, however,might render the implementation of higher order filters impractical.It has been shown in [2] that a high performance FIR filter with substantial number of taps can be implemented on FPGAs by approximating the filter coefficients to a sum or difference of two poweroftwo terms. Implementation of digital filters may be simplified by using only a limited number of poweroftwo terms so that only a small number of shift and add operations is required. A variety of techniques have been proposed [15, 16] to minimize the deterioration of the frequency response due to these constraints. Such coefficient optimization techniques yield performance sufficient for most practical applications.. Moderate Performance Filters on FPGAsWhen the size of the chip is a constraint, the arithmetic resources need to be shared at the expense of speed. The structure shown in Figure 7 is suitable for sharing of arithmetic resources. This is a multiply/accumulate (MAC) unit with four multipliers and an adder tree. The inputs and the corresponding filter coefficients are fed to the MAC unit as shown in Figure 7. With the insertion of pipeline registers, the clock speed is increased. The delay in the multiplier is greater than that in the adder and hence the clock frequency is dependent on the delay in the multiplier. As there are four multipliers in this MAC unit, summation of four terms isputed every clock cycle. Hence a four tap filter can be made to operate at a sampling rate equal to the clock rate, and an eight tap filter to operate at a sampling rate half that of the clock rate.In general, if there are M multipliers in a chip and if the delay in the multiplier is Tsec, then an N tap filter can operate at a maximum sampling frequency fs given byAn implementation based on the multipleinput MAC unit, as shown in Figure 7,was used to evaluate this moderate performance approach to the realization of a filter with an arbitrary number of taps. The placement of the MAC unit on a Xilinx XC4010 is shown in Figure 8. The four multipliers are arranged in the four corners of the 20 by 20 array of CLBs to reduce the delay from the input pins to the multipliers. Inputs to the multipliers are fed in at right angles, as explained previously, and the arrays are oriented in such a way that the routing delays from pads are minimized. For ease of understanding, the most significant bit (M), intermediate bit (I), and least significant bit (L) of the output of each multiplier are marked in the Figure. The four adders were arranged vertically to exploit the dedicated carry logic supported by the XC4000 series. The size of the chip limited the number of multipliers to four. Four columns of CLBs were left for the adders. The three intermediate adders were provided with the required number of bits, that is, 16 bits, 16 bits, and 17 bits, respectively. The adders were arranged in two columns as shown in Figure 8. This leaves two full columns capable of supporting more than 70 bits for the final adder and provides sufficient intermediate word width protection for most applications.The routing between the arithmetic elements is not critical becausethe delay in the multiplier is 100 ns and that in the adder is ns (for a 16 bit adder) which allows routing delays to be as large as 75 ns without affectin