【正文】 he total number of CLBs used for the multiplier in this case is 64 and the basic cell structure is illustrated in Figure 2.Each cell is configured as a full adder (except for the type A cell). This full adder accepts a sum and a carry from a previous operation of equal weight, as shown in Figure 2, and the logical AND of the inputs xi and ai.The sum and carry generated by the adder are then sent to the CLBs of proper weight as shown in Figure 3. The multiplier has been configured to perform multiplication of signed numbers in two’s plement notation. The small circles in the figure indicate negative inputs or outputs。 重慶大學(xué)本科學(xué)生畢業(yè)設(shè)計（論文）附件 附件D：FPGA IMPLEMENTATION OF DIGITAL FILTERSChiJui Chou, Satish Mohanakrishnan, Joseph B. EvansTelemunicationsamp。 Information Sciences LaboratoryDepartment of Electrical amp。 such bits have to be subtracted rather than being added. The cells in the leftmost column of the array only AND their two inputs and generate the product. If one of the two inputs has a negative weight, then the output will have a negative weight. The conventional 1bit full adder assumes positive weights on all of its 3 inputs and 2 an adder can be generalized to four types of adder cells by attaching positive and negative weights to the input/output pins as discussed in [7]. Figure 4 lists the logic symbols for the fourtypes of generalized full adders.The Boolean equations governing the Type 0 and 3 full adders areand those for the Type 1 and 2 adders areType 0 and Type 3 full adders are characterized by the same pair of logic equations, identical to that of the conventional 1bit full adder (Type 0). This is becausea Type 3 full adder can be obtained from a Type 0 full adder by negating all of the input and output values and vice versa. A similar relationship can be established between Type 1 and Type 2 full adders. For Type 0, 1, 2, and 3 full adders, the two independent 4bit functions were used to generate the sum and carry outputs. We can easily include the AND gate in the CLB just by replacing, for example, X with(xi and ai) when configuring the CLB. The horizontal inputs(xi,ai) can use the horizontal longlines which are associated with each row for distribution of the signal with a very short routing delay. Other interconnections can be made using the singlelength or doublelength lines via ProgrammableInterconnection Points (PIP) or switching matrices.. Adder ImplementationIn the XC4000 series, each CLB includes highspeed carry logic that can be activated by configuration. The two 4input functionGenerators may be configured as a 2bit adder with builtin hidden carry that can be expanded to any length. The 16bit adder in our MAC unit, which uses the dedicated carry logic, requires nine CLBs. The middle 14bits use 7 CLBs, one CLB is used for the MSB, and one is used for the LSB of the adder. For each CLB in the middle section, the F function is used for lowerorder bit and the G function is used for higherorder bit. Obviously, we need to use the G function for the LSB bit and F function for the MSB bit. In the case of the LSB CLB, two values must be input on the G1 and G4 pins. The carry signal enters on the F1 pin,propagates through the G carry logic, and exits on the COUT pin. The F function of this CLB is not used and can be used for other purposes. For the middle CLBs, the logic is configured to perform a 2bit addition of A+B in both the F and G functions,with the lowerorder A and B inputs on the F1 and F2 pins, andthe higherorder A and B inputs on the G1 and G4 pins. The carry signal enters on the CIN pin, propagates through the F and G carry logic, and exits on the COUT pin. For the MSB CLB, the two values must be input on F1 and F2 pins. The carry signal enters on the CIN pin, propagates through the F carry logic, and exits on the COUT pin. The G function generator of this CLB is used to access the carry out signal or calculate a two’s plement overflow.The limitation of using this builtin carry logic is that the carry out (COUT) pin of a CLB can only be connected to the carry in (CIN) pin of the CLBs above or below. Thus the adder using fast carry logic can only be configured vertically in the array.The dedicated carry circuitry greatly increases the efficiency and performance of adders. Conventionalmethods for improving performance such as carry generate/propagate are not useful even at 16bit level, and are of marginal benefit at longer our case, the 16bit adder has a binatorial delay of only ns.. MAC ImplementationWe use the most significant 8 output bits of the multiplier as the input to the low order bits of the adder. The 8bit input of the adder is signextended and added with previous outputs using two’s plement addition.The basic structure of the MAC unit can use pipeline registersbetween the multiplier and accumulator to increase the flipflops in the CLBs are used as pipeline registers and hence noadditional CLBs are needed.The layout of a single MAC unit on an XC4000series part isshown in Figure 5.The performance of the MAC unit with an 8bit by 8bit multiply and 16 bit accumulator is determined by the speed of the multiplier. The worst case multiplier delay reported is approaching 100 ns. The MAC unit can thus support a clock speed better than 10 MHz. With the use of the horizontal longlines to distribute the critical path signals, the speed can be further improved,although this may restrict the use of the MAC unit in various system configurations. The implementation of a MAC unit on an XC4000series part requires 73 CLBs. FILTERS. Filter StructuresThe transfer function of an N tap FIR filter is given by This structure can be realized in many ways, such as the canonical form, pipelined form, and inverted form as depicted in Figure 6. . High Performance Filters on FPGAsThe inverted form shown in F