【正文】 ent main FPGA is still based on lookup table technology, has far exceeded the previous version of the basic performance, and integrate the mon functions (such as RAM, clock management and the hardcore (DSP) ASIC type) module. The FPGA chip partially pleted by 7 to Lord, respectively: programmable input/output unit, basic programmable logic unit, plete clock management, embedded pieces type RAM, rich wiring resources, embedded bottom function units and inline dedicated hardware modules. The function of each module are as follows: 1. Programmable input/output unit (IOB) Programmable input/output unit referred to as I/O unit, is the interface with external circuit chip, plete different part electrical characteristics of input/output signal driver and matching requirements, its beckoned structure shown as shown in figure 12. The I/O within the FPGA in groups, each of classification can be independently support different I/O standards. Through the flexible configuration software can fit different electrical standards and I/O physical properties, can adjust the drive current size, can change, pulldown resistor. At present, the frequency of I/O port more and more is also high, some highend FPGA technology can support by DDR 2Gbps registers as the data rate. External input signal can through the storage unit IOB module input into the FPGA interior, may also enter the FPGA internal. When external input signal after IOB module ? the storage unit. To facilitate the management and adapt to a variety of electric equipment standard, FPGA IOB was divided into the several group (the somebody), each by its interface standard somebody VCCO decision, a interface voltage somebody there can be only one of VCCO, but different VCCO can differ to somebody. Only the same electrical standard ports to connect together, VCCO voltage is the basic condition of interface standards. 畢業(yè)設(shè)計(jì)（論文）專用紙 第 頁(yè) 17 2. Configurable logic block (CLB) CLB is the basic logic unit within the FPGA. The actual number of CLB of the device and the characteristic will depend on different and different, but each CLB contains a configurable, the matrix switching matrix by four or six input, some selection circuits (multiplexing machines etc) and trigger position. A switching matrix is highly flexible, open to configuration so that treatment binations logic, the shift register or RAM. Xilinx FPGA device in the pany, by multiple (CLB is generally four or 2) the same Slice and additional logic structure, as shown in figure 13 below. Each CLB module can not only used to implement the binational logic, temporal logic, also can be configured to distributed RAM and distributed ROM. Xilinx Slice is the basic logic unit the definition, its internal structure as shown in figure 14 shows, a Slice of by two 4 functions, binary input in logic, calculate ? 3. Digital clock management module (DCM) This provides the most FPGA digital clock management (all have Xilinx FPGA nature of this). Xilinx FPGA provide the most advanced launched digital clock management and phase lock loop. Phase lock loop can provide precise clock prehensive, and can reduce jitter, and realize the filter function. 4. Embedded blocks RAM (BRAM) Most FPGA have nested block RAM, which greatly expand the application range of the FPGA and agility. Block RAM can be configured to single port RAM, twoport RAM, content address memory (CAM) and FIFO storage structure some. RAM, FIFO is the concept of is popular in this was not redundant, description. CAM memory in its internal every single YuanZhongDou has a paratively stored data in logic, writing CAM and internal each data, and returns pared with all the same port data, thus the address of data in the routing address switch is widely used. In addition to block RAM, still can place the LUT flexibly FPGA RAM and 畢業(yè)設(shè)計(jì)（論文）專用紙 第 頁(yè) 18 ROM and configured structures such as FIFO. In practical application, the number of RAM chip internal pieces of choice chip is an important factor. Monolithic block RAM has a capacity of 18k bits, took the wide for 18 to bits, depth for 1024, and may, according to needs to change its position, but should satisfy harnessed two principles: first, the revised capacity (a wide depth) is not greater than 18k bit。 x老師的熱心給予的完成畢業(yè)設(shè)計(jì)的動(dòng)力， x老師的幫助使我客服了諸多困難，最終在老師的指導(dǎo)下我完成了畢業(yè)設(shè)計(jì)，再次我要深深的感謝她。在大學(xué)期間學(xué)院給我們專業(yè)開(kāi)了不少課程，自己沒(méi)怎么認(rèn)真學(xué)習(xí)，這一點(diǎn)在平時(shí)沒(méi)怎么感受，但是在這次的畢業(yè)設(shè)計(jì)中我我卻感受到了。 當(dāng)然在設(shè)計(jì)過(guò)程中也遇見(jiàn)了不少自己解決不了的問(wèn)題，對(duì)此我很感謝我的老師、同學(xué)們的幫助。 （ 3）本設(shè)計(jì)重點(diǎn)在于軟件的設(shè)計(jì)，因此在設(shè)計(jì)過(guò)程中使自己在大學(xué)學(xué)到的 Verilog語(yǔ)言知識(shí)得到了鞏固，同時(shí)提高了解決實(shí)際問(wèn)題的能力 畢業(yè)設(shè)計(jì)（論文）專用紙 第 頁(yè) 11 總結(jié)與體會(huì) 通過(guò)幾個(gè)月的努力，萬(wàn)年歷設(shè)計(jì)基本完成了所要實(shí)現(xiàn)的功能，完成了畢業(yè)設(shè)計(jì)。這次畢業(yè)設(shè)計(jì)可以說(shuō)是對(duì)四年的大學(xué)學(xué)習(xí)的總結(jié)。但使用這種紙質(zhì)日歷，必須記得每天按時(shí)撕一張，否則反而會(huì)記錯(cuò)日 期，常常有人因?yàn)橥浢刻焖旱舳涘e(cuò)日期，錯(cuò)過(guò)重要事情，造成損麻煩。 畢業(yè)設(shè)計(jì)（論文）專用紙 第 頁(yè) 9 第 4 章 模擬仿真 年月日模塊仿真 該仿真圖顯示的是 09年 5月分的，由圖可以看出 5月分有 31天，當(dāng)月份進(jìn)入到下一個(gè)月的時(shí)候，日期 day則變?yōu)?1號(hào)，仿真結(jié)果無(wú)誤。當(dāng) k是低電平時(shí)，該模塊的輸出端輸出的是年月日，即：令 q0、 q q q3顯示年信號(hào)的千位、百位、十位、個(gè)位， q q5顯示月信號(hào)的十位與個(gè)位， q q7顯示日信號(hào)的十位與個(gè)位。這里不再多說(shuō)。這里有個(gè)需要注意的是 2月，一般年份 2月有 28天，但是閏年則有 29天。 畢業(yè)設(shè)計(jì)（論文）專用紙 第 頁(yè) 7 年月日模塊（ nyr2020） 日計(jì)數(shù)：日信號(hào) qr[7:0]，日進(jìn)位信號(hào) clky，以及每月天數(shù) date。則當(dāng)時(shí)信號(hào)計(jì)數(shù)到 23(qsh==2amp。 如果 qfh5， qfl==9，則 qfh=qfh+1， qfl=0， carry1=0；如果 qfh5， qfl9，則 qfh=qfh，qfl=qfl+1， carry1=0。 分（ minute）：分信號(hào) qf[7:0]，低四位 qfl[3:0]，高四位 qfh[7:0]，分進(jìn)位信號(hào)enhour。給予秒信號(hào)和進(jìn)位信號(hào)一個(gè)初始值，令 {qmh,qml}=0,carry1=0。當(dāng)按下外部按鍵的時(shí)候，也就意味著使用者參與控制了，該模塊有 2個(gè)外置按鍵可供使用者使用，按下第一個(gè)按鍵則顯示時(shí)分秒，按下第二個(gè)按鍵顯示年月日，當(dāng)兩個(gè)按鍵都按下的時(shí)候默認(rèn)按鍵無(wú)效。 系統(tǒng)設(shè)計(jì)圖 畢業(yè)設(shè)計(jì)（論文）專用紙 第 頁(yè) 4 圖 1 流程圖 圖 2 功能設(shè)計(jì)圖 畢業(yè)設(shè)計(jì)（論文）專用紙 第 頁(yè) 5 第 3 章 各功能模塊介紹 分頻模塊（ fenpin） 該模塊的主要功能是想得到一個(gè)時(shí)鐘頻率為 1Hz的一個(gè)脈沖，也就是說(shuō) 想得到周期為 1秒的一個(gè)脈沖。與那些內(nèi)部功能已被制造者固化的器件相反。