【文章內(nèi)容簡介】 畢業(yè)設(shè)計（論文）專用紙 第 頁 11 總結(jié)與體會 通過幾個月的努力，萬年歷設(shè)計基本完成了所要實現(xiàn)的功能，完成了畢業(yè)設(shè)計。在這次的設(shè)計過程中主要 是在 Quartus2上使用 Verilog語言完成代碼的編寫與模擬仿真，在設(shè)計過程中出現(xiàn)了不少的問題，一些問題是因為自己的粗心大意，也有一些問題則是對相關(guān)知識的認識不夠徹底。通過對這些問題的解決處理，我感覺到不僅所學(xué)知識有了較全面的了解，同時也是對我自身的一個進步。比如開始我沒能認真書寫導(dǎo)致出現(xiàn)不少錯誤字符，沒能及時保存導(dǎo)致文檔丟失等，這些問題的發(fā)現(xiàn)解決我相信對我以后進入社會，參加工作是一個很好的鍛煉。 當(dāng)然在設(shè)計過程中也遇見了不少自己解決不了的問題，對此我很感謝我的老師、同學(xué)們的幫助。他們的幫助不僅使我順利 解決問題，同時也使我感受到了溫暖，給了我強大的動力，使我和同學(xué)們的關(guān)系更加緊密，使我更加深入明白了團結(jié)就是力量。我相信在以后的人生道路上，我將不會迷茫，因為我知道我不能解決的問題不一定是不能解決的問題，這一點我堅信。 最后我想說的是我又一次感受到了書到用時方恨少。在大學(xué)期間學(xué)院給我們專業(yè)開了不少課程，自己沒怎么認真學(xué)習(xí)，這一點在平時沒怎么感受，但是在這次的畢業(yè)設(shè)計中我我卻感受到了。畢業(yè)設(shè)計是對大學(xué)以往知識的綜合運用，但是由于學(xué)習(xí)的不夠認真，導(dǎo)致這設(shè)計過程中遇見了很多看似簡單卻沒法自我完成的問題。 畢業(yè)設(shè)計（論文）專用紙 第 頁 12 謝辭 該畢業(yè)設(shè)計在一定程度上代表了我大學(xué)四年所學(xué)，也是我大學(xué)生活的一個結(jié)束，為此我想在這里感謝學(xué)院為我?guī)淼囊磺?，沒有學(xué)院為我提供的這個平臺，我想將會很難順利地完成大學(xué)四年的學(xué)習(xí)和本次畢業(yè)設(shè)計。 該論文 是在我的畢業(yè)設(shè)計指導(dǎo)老師 x老師的親切、熱心的指導(dǎo)下完成的。 x老師的熱心給予的完成畢業(yè)設(shè)計的動力， x老師的幫助使我客服了諸多困難，最終在老師的指導(dǎo)下我完成了畢業(yè)設(shè)計，再次我要深深的感謝她。 同時，我還要感謝 x老師，在做畢業(yè)設(shè)計的過程中我深深的感到了在去年和 x老師一起學(xué)習(xí) Quartus2對于我的畢業(yè)設(shè)計是多么的有用。 所以我要感謝 x老師。 在設(shè)計之初，我的迷茫曾一度讓我煩悶，不知道該怎么寫，不知道怎么下手，在這個困難時期，各位老師和同學(xué)給了我很大的幫助，使他們的幫助使我一步步的完成了畢業(yè)設(shè)計。在這里請接受我真誠的謝意！ 畢業(yè)設(shè)計（論文）專用紙 第 頁 13 參考文獻 [1] 劉建清，劉漢文，高光海，等，從零開始學(xué) CPLD和 VerilogHDL編程技術(shù) [M]，北京：國防工業(yè)出版社， 2020； [2] 楊春玲，朱敏，等，可編程邏輯器件應(yīng)用實踐 [M]，哈爾濱：哈爾濱工業(yè)大學(xué)出版社， 2020 [3] 馮濤，王程，等，可編程邏輯器件開發(fā)技術(shù) —— MAX+plus2入 門與提高 [M]，北京：人民郵電出版社， 2020 [4] 杜海生，邢文等， FPG設(shè)計指南器件、工具和流程 [M]，北京：人民郵電出版社， 2020 [5] 王輝，殷穎，陳婷，俞一鳴，等， MAX+plus2和 Quattur2應(yīng)用于技巧開發(fā) [M]，北京：機械工業(yè)出版社， 2020 [6] 張志剛，等， FPGA于 SOPC設(shè)計教程 —— DE2實踐，西安：西安電子科技大學(xué)出版社， 2020 [7] 夏宇聞，等， Verilog數(shù)字系統(tǒng)設(shè)計教程（第 2版） [M]，北京：北京航空航天大學(xué)出版社， 2020 [8] 鄭利浩，王荃，陳華鋒，等 ， FPGA數(shù)字邏輯設(shè)計教程 —— Verilog[M]，北京：電子工業(yè)出版社，2020 [9] 夏宇聞，甘偉，等， Verilog HDL入門 (第 3版 )[M]，北京：北京航空航天大學(xué)出版社， 2020 [10]吳厚航，等，深入淺出玩轉(zhuǎn) FPGA[M]，北京：北京航空航天大學(xué)出版社， 2020 [11]吳繼華，王誠，等， Altera FPGA/CPLD設(shè)計（基礎(chǔ)篇），北京：人民郵電出版社， 2020 [12] EDA先鋒工作室，吳繼華，蔡海寧，王誠，等， Altera FPGA/CPLD設(shè)計（高級篇）（第 2版），北京：人民郵 電出版社， 2020 [13]（美）沃爾夫（ Wolr,W.），等，基于 FPGA的系統(tǒng)設(shè)計 [M]，北京：機械工業(yè)出版社， 2020 [14]姚遠，李辰，等， FPGA應(yīng)用開發(fā)入門與典型實例（修訂版） [M]，北京：人民郵電出版社， 2020 [15]侯伯亨 ,等， VHDL硬件描述語言與數(shù)字邏輯電路設(shè)計（第三版） [M]，西安：西安電子科技大學(xué)出版社， 2020 畢業(yè)設(shè)計（論文）專用紙 第 頁 14 附錄一 At present by the hardware description language (Verilog or VHDL) has done by a simple circuit design, can the prehensive and layout, rapid replication to test, is on the FPGA design verification of modern IC technical mainstream. These can edit ponent can be used to achieve some basic logic gate (such as AND, OR, XOR, NOT) OR a bit more plicated bination function such as decoder OR mathematical equations. In most of the FPGA inside, these editable ponents are contains memory ponents such as flipflop Flip flop) (or other more plete memory blocks. System according to need stylist can be connected by editable the FPGA internal logic, like connecting block a circuit test plate is placed on a chip. A after they leave the finished product FPGA logic blocks and connection can be changed according to the designers, so the FPGA can plete need logical functions. The FPGA in general than ASIC (special integrated chips) speed will slow, unable to perform plex designs, and consume more power. But they also have many advantages such as can quickly finished product, can be modified to correct an error in a programme and cheaper cost. Manufacturers might also offer cheap but editing ability is poor FPGA. Because these chips have more bad of the editable ability, so these design development is in ordinary FPGA pletion, and then on to design transferred to a similar to the chip ASIC. Another method is to use CPLD (plex programmable logic device prepare). Early in the mid 1980s PLD equipment in FPGA has root. CPLD and FPGA includes some relatively large number of programmable logic unit. CPLD logical gate 畢業(yè)設(shè)計（論文）專用紙 第 頁 15 density in a logical units to tens of thousands, and FPGA is usually between in tens of thousands to millions of. The major difference between and FPGA CPLD their system structure. CPLD is a bit of restrictive structure. This structure by one or more editable results logical groups of the sum of gilead and some relatively low amounts of locking registers. The result is that lack of editing flexibility, but there can be expected to delay time and logic unit link units a high rate of advantages. And there are many connection FPGA is, so although let it unit can be more flexible editor, but the structure are much more plex. CPLD and FPGA another difference is most FPGA contain high levels of builtin module (such as adder and on timemultiplier) and builtin memory. A so the important difference is concerned, many new FPGA support full or part of the system in a configuration. Allow their design with system upgrades or dynamic reconfigured and change. Some FPGA can let equipment edit and part of the normal operation. Other parts continue. By the Logic element Array FPGA LCA (Array) such a Cell questions concept, internal including Configurable Logic module which CLB (Configurable questions) and Output Input module which Output IOB (Input) and internal attachment (Interconnect) three parts. Field programmable gates array (FPGA) is programmable devices. And the traditional logic circuit and the gate array (such as PAL GAL and CPLD device), pared with different structure, the FPGA, FPGA with small lookup table (16 x 1RAM) to realize the bination of logic, each lookup table connected to a D flipflop input and trigger again drive other logic circuit or driver I/O, which constitutes the assembly logic functions can be realized and realize the basic logic sequential logical function module, these module unit by using metal connection between interconnected or connected to the I/O modules. The logic is through FPGA inward. 畢業(yè)設(shè)計（論文）專用紙 第 頁 16 Current main FPGA is still based on lookup table technology, has far exceeded the previous version of the b