【正文】 畢業(yè)設(shè)計 (論文 ) I 基于 CPLD 的頻率測量計 摘 要 本文主要論述了利用 CPLD 進(jìn)行測頻計數(shù)，單片機(jī)實(shí)施控制實(shí)現(xiàn)等精度頻率計的設(shè)計過程。該頻率計利用等精度的設(shè)計方法，克服了基于傳統(tǒng)測頻原理的頻率計的測量精度隨被測信號頻率的下降而降低的缺點(diǎn)。等精度的測量方法不但具有較高的測量精度，而且在整個頻率區(qū)域保持恒定的測試精度。該頻率計利用 CPLD 來實(shí)現(xiàn)頻率的測量計數(shù)。利用單片機(jī)完成整個測量電路的測試控制、數(shù)據(jù)處理和顯示輸出。 本文詳細(xì)論述了硬件電路的組成和單片機(jī)的軟件控制流程。其中硬件電路包括鍵控制模塊、顯示模塊、輸入信號整形模塊以 及單片機(jī)和 CPLD 主控模塊。設(shè)計器件采用Atmel 公司的單片機(jī) AT89C51 和 Altera 公司的 MAX7000 系列 EPM7128SLC8415 芯片 。鍵控制模塊設(shè)置 1 個開始鍵和 3 個時間選擇鍵，鍵值的讀入采用一片 74LS165 來完成；顯示模塊用 8 只 74LS164 完成 LED 的串行顯示；被測信號經(jīng)限幅后由兩級直接耦合放大器進(jìn)行放大，再經(jīng)施密特觸發(fā)器整形后輸入 CPLD；標(biāo)準(zhǔn)頻率采用 40MHz 有源晶振動實(shí)現(xiàn)；單片機(jī)軟件用匯編語言編寫，軟件模塊對應(yīng)于硬件電路的每一個部分，還包括部分?jǐn)?shù)據(jù)計算和轉(zhuǎn)換模塊。 關(guān)鍵詞： 單片機(jī) ， CPLD， 頻率計 ， 測頻 ， 等精度 畢業(yè)設(shè)計 (論文 ) II THE DESIGN OF FREQUENCY MEASUREMENT BASED ON CPLD Abstract The reach pape rmainly discusses the design process of equalaccuracy frequency meter that uses CPLD to count the frequency measurement and frequency meter is also controled by single chip puter. The frequency meter makes use of equalaccuracy design that can overe the disadvantage of traditional measuring principle, which precision declines as measured signal frequency does. The equalaccuracy measurement not only has higher measuring precision, but also can keep invariable measuring precision in whole area of frequency meter uses CPLD to realize the measuring count of frequency. Single chip puter pletes the test control、 data processing and display output of the system. This essay discusses the pose of hardware circuit and software control flow of single chip puter in detail. Hardware circuit includes key control module、 display module, plastic module of input signal、 single chip puter control module and CPLD main control frequency meter adopts single chip puter AT89C51 of Atmel pany and EPM7128SLC8415 of Altera pany. Key control module has 1 function key and 3 time selection key. A chip 74LS165 pletes the key value input. Display module uses eight 74LS165s to realize the serial display of LED. First, the measuring signal amplitude is limited. Second, the single is amplified by two class direct coupling amplifier. Finally, the signal inputs CPLD after it is trimed by Smitter trigger. Standard frequency is 40MHz. Software program of single chip puter is writed by assembly language. Some of software program is corresponded to every hardware part, the others includ data count and transform . Ke y Words： SCM。CPLD， Frequency meter， Frequency measurement， Equalprecision 畢業(yè)設(shè)計 (論文 ) III 目錄 第一章 引言 ............................................................................................................................. 1 第二章 測量原理及其設(shè)計內(nèi)容 ............................................................................................. 2 測量原理 ................................................................................................................... 2 頻率計的設(shè)計內(nèi)容和意義 ....................................................................................... 3 第三章 硬件電路設(shè)計 ............................................................................................................. 6 系統(tǒng)組成 ................................................................................................................... 6 測頻模塊的工作原理及設(shè)計 ................................................................................... 7 CPLD 的結(jié)構(gòu)與功能介紹 ............................................................................. 7 CPLD 測頻模塊的邏輯設(shè)計 ......................................................................... 8 鍵控制模塊 ............................................................................................................. 10 顯示模塊 ................................................................................................................. 11 電源模塊 ................................................................................................................. 12 輸入信號整形模塊 ................................................................................................. 13 單片機(jī)主控模塊 ..................................................................................................... 14 AT89C51 單片機(jī)性能 ................................................................................. 14 單片機(jī)控制電路 .......................................................................................... 16 其它電路 ................................................................................................................. 18 第四章 軟件設(shè)計 ................................................................................................................... 19 Quartus II 概述 ........................................................................................................ 19 Quartus II 使用 VHDL 實(shí)現(xiàn)系統(tǒng)功能的全過程 ................................................... 20 電子系統(tǒng)的設(shè)計方法 .................................................................................. 20 “自頂向下”與“自底向上”的設(shè)計方法 .............................................. 21 VHDL 語言簡介 .......................................................................................... 22 頻率計的 VHDL 設(shè)計 ................................................................................. 22 CPLD 模塊仿真 ...................................................................................................... 25 單片機(jī)的匯編語言編程 ......................................................................................... 26 單片機(jī)主程序 .............................................................................................. 26 畢業(yè)設(shè)計 (論文 ) IV 測頻子程序 .................................................................................................. 27 顯示子程序 .................................................................................................. 28 鍵盤掃描子程序 .......................................................................................... 29 時間值輸入子程序 ...........................................................