【正文】 理工大學學士學位論文 I 摘 要 隨著計算機在人們生活中重要性和不可或缺性的提高，為了更方便的為大眾使用，發(fā)展計算機性能成為 IT 行業(yè)的熱點，但計算機的內部結構極其復雜，為了便于研究便產生了模型計算機。 本文完成了基于 VHDL的 8 位模型計算機的設計與實現(xiàn)。文中首先闡述了 8 位模型計算機的原理，然后對其十個功能模塊（算術邏輯運算單元，累加器，控制器，地址寄存器，程序計數(shù)器，數(shù)據(jù)寄存器，存儲器，節(jié)拍發(fā)生器，時鐘信號源，指令寄存器和指令譯碼器）進行了分析與設計。最后在 Quartus II 環(huán)境下進行了仿真，完成了 8 位模型計算機的整 體實現(xiàn)。 本文綜合了計算機組成原理和數(shù)字邏輯與系統(tǒng)設計的知識， 設計的 8 位模型計算機能更方便的了解計算機內部構造和工作原理。整個系統(tǒng)的開發(fā)體現(xiàn)了在 Quartus II 軟件平臺上用 VHDL設計數(shù)字控制系統(tǒng)的實用性。 關鍵詞 ： 8 位模型機 ； Quartus II ； VHDL語言 理工大學學士學位論文 II Abstract With the improvement of importance and indispensability in puter in people39。s life,in order to use more conveniently for public ,puter performance is being a hot in the IT industry the internal structure of the puter is very plicate,Computer model simplifies the difficulty of the research. This article pleted the design and implementation of eight model puter based on ,this article expounds the principle of eight model puter,then divides it into 10 modules(arithmetic logic unit, accumulator, controllers, address register, the program counter and data registers, memory, beat generator, a clock signal, instruction register and instruction decoder)and analyse and design each of under the environment of the Quartus II simulation, pleted overall implementation of the 8 model puter. The analysis and design of the eight model puter integrated the knowledge of puter constitute principle and Digital logic and system design. The design of the eight model puter can be more convenient to understand internal structure and working whole system development manifests the practicability of designing the numerical control system on the Quartus II software platform with VHDL. Key words: eight model puter 。 VHDL language。 Quartus II 理工大學學士學位論文 III 目 錄 1 緒論 ...................................................................................................................................... 1 本課題研究的目的 .................................................................................................... 1 本課題研究的背景及意義 ........................................................................................ 1 2 基于 VHDL編程的基礎知識 ............................................................................................. 4 VHDL 語言概述 ........................................................................................................ 4 VHDL 的設計流程 .................................................................................................... 5 有關 Quartus II 的介紹 ............................................................................................. 6 本課題基于 Quartus II 的設 計流程 .......................................................................... 8 3 基于 VHDL8 位模型機的原理與設計 ............................................................................... 9 模型計算機的原理 .................................................................................................... 9 模型機的總體設計要求 ............................................................................................ 9 模型機邏輯框圖的設計 .......................................................................................... 10 模型機的指令系統(tǒng)設計 .......................................................................................... 10 模型機的指令執(zhí)行流程設計 .................................................................................. 11 基于 VHDL8 位模型機各模塊的設計與實現(xiàn) ....................................................... 12 算術邏輯單元 ALU模塊 .............................................................................. 12 累加器模塊 .................................................................................................... 14 控制器模塊 .................................................................................................... 18 節(jié)拍發(fā)生器 .................................................................................................... 21 指令寄存器模塊 IR 和指令譯碼器 .............................................................. 24 時鐘產生器 .................................................................................................... 28 程序計數(shù)器模塊 ............................................................................................ 30 地址寄存器 MAR .......................................................................................... 33 存儲器 RAM .................................................................................................. 36 數(shù)據(jù)寄存器 DR............................................................................................ 38 4 基于 VHDL的 8 位模型計算機的實現(xiàn) ........................................................................... 42 基于 VHDL的微程序執(zhí)行流程圖 ......................................................................... 42 8 位模型機的頂層原理圖設計 ............................................................................... 43 理工大學學士學位論文 IV 基于 VHDL的 8 位模型機工作流程 ..................................................................... 44 頂層 VHDL源程序設計 ......................................................................................... 45 頭文件 cpu_defs 的 VHDL 設計 ................................................................... 45 CPU的 VHDL源程序設計 .......................................................................... 46 8 位模型機的整體實現(xiàn) ........................................................................................... 54 結 論 ........................................................................................................................................ 57 致 謝 ........................................................................................................................................ 58 參考文獻 .................................................................................................................................. 59 附錄 A 英文原文 ..........................