【正文】 lows the modification of the operation of the device through simple reprogramming. The primary limitations of FPGAs are related to the overhead imposed by programmability. In particular, the density of the devices is only now reaching the level necessary to implement plete modules of reasonable plexity. Other difficulties associated with the devices result from the constraints imposed by the architecture, such as limitations on the logic functions which may be implemented in each logic block, and routing delays in the array. Many of these difficulties can be overe by careful design. Due to everincreasing integrated circuit fabrication capabilities,the future of FPGA technology promises both higher densities and higher speeds. Many FPGA families are based on memory technology, so the improvements in those areas should correlate with FPGA evolution. The expanded use of FPGAs in a variety of challenging application domains is thus likely. FPGAs are well suited for the implementation of fixedpoint digital signal processing algorithms. The advantages of DSP on FPGAs are primarily 附件 D：譯文原文 D4 related to the additional flexibility provided by FPGA reconfigurability. Not only can highperformance systems be implemented relatively inexpensively, but the design and test cycle can be pleted rapidly due to the elimination of the integrated circuit fabrication delays. The new approach also allows adapting the functions to account for unforeseen problems of DSP on FPGAs are related to the density and routing constraints imposed by the FPGA architectures. In particular,the number of logic gates which may be implemented on an single device, and hence the number of arithmetic units, is still limited, and the routing between modules on an array imposes the critical delay limitations. Because of the constraints imposed by FPGAs, implementation of digital filter algorithms through this medium must initially focus on efficient structures which possess low plexity [2].Concurrent design of efficient digital filter algorithms and FPGA implementations is necessary to take full advantage of the new capabilities. In this particular work, Xilinx XC4000series FPGAs were used to implement various digital filter algorithms and evaluate their performance. A Xilinx XC4000 consists of an array of configurable logic blocks (CLBs), each of which has several inputs(F1F4, G1G4) and outputs (X,Y and XQ,YQ). Each CLB can contain both random logic and synchronous elements. In addition to the generalpurpose logic functions, each CLB also contains special fast carry logic for addition operations. The XC4000series contains both local and global routing resources. The local resources allow extremely low delay interconnection of CLBs within the same neighborhood, as well as more extended connection through the use of switching matrices. The global resources provide for the lowdelay distribution of signals that are used at widelyspaced points in the array. The speed of a particular application is highly dependent on routing in the Xilinx FPGAs. The XC4000 family includes parts ranging from 8 by 8 CLB arrays to 24 by 24 CLB arrays. All of these devices are insystem power versions of many of these parts are also available. 3. MULTIPLYACCUMULATE UNITS Several authors [1, 11, 12, 13] have identified the multiply accumulate (MAC) operation as the kernel of various digital signal processing 重慶大學(xué)本科學(xué)生畢業(yè)設(shè)計(jì)（論文）附件 D5 algorithms. A variety of approaches to the implementation of the multiplication and addition portions of the MAC function are possible [7, 10]. This work will focus on the realization of multiplication using an array approach and addition using ripple carry methods, although other methods are equally applicable to the FPGA domain. The structure of a MAC unit is illustrated in Figure 1. The MAC unit presented in this section consists of an 8bit by 8bit binatorial array multiplier and a 16bit accumulator. These word sizes were chosen to balance the size of the implementation,which is limited by the FPGA density, against the numerical precision. Larger word sizes are possible if the number of MAC units per chips is reduced. The increase in density of FPGAs in the future will certainly expand the design space available to the designer, and make such constraints less severe. . Implementation of Multiplier The binatorial multiplier uses one CLB per partial product bit. A 2inputAND gate generates each partial product, but additional 附件 D：譯文原文 D6 circuitry is required to add together all partial products of equal weight. The total number of CLBs used for the multiplier in this case is 64 and the basic cell structure is illustrated in Figure 2. Each cell is configured as a full adder (except for the type A cell). This full adder accepts a sum and a carry from a previous operation of equal weight, as shown in Figure 2, and the logical AND of the inputs xi and ai. The sum and carry generated by the adder are then sent to the CLBs of proper weight as shown in Figure 3. The multiplier has been configured to perform multiplication of signed 重慶大學(xué)本科學(xué)生畢業(yè)設(shè)計(jì)（論文）附件 D7 numbers in two’s plement notation. The small circles in the figure indicate negative inputs or outputs。 such bits have to be subtracted rather than being added. The cells in the leftmost column of the array only AND their two inputs and generate the product. If one of the two inputs has a negative weight, then the output will have a negative weight. The conventional 1bit full adder assumes positive weights on all of its 3 inputs and 2 an adder can be generalized to four types of adder cells by attaching positive and negative weights to the input/output