【正文】 only can highperformance systems be implemented relatively inexpensively, but the design and test cycle can be pleted rapidly due to the elimination of the integrated circuit fabrication delays. The new approach also allows adapting the functions to account for unforeseen problems of DSP on FPGAs are related to the density and routing constraints imposed by the FPGA architectures. In particular,the number of logic gates which may be implemented on an single device, and hence the number of arithmetic units, is still limited, and the routing between modules on an array imposes the critical delay limitations. Because of the constraints imposed by FPGAs, implementation of digital filter algorithms through this medium must initially focus on efficient structures which possess low plexity [2].Concurrent design of efficient digital filter algorithms and FPGA implementations is necessary to take full advantage of the new capabilities. In this particular work, Xilinx XC4000series FPGAs were used to implement various digital filter algorithms and evaluate their performance. A Xilinx XC4000 consists of an array of configurable logic blocks (CLBs), each of which has several inputs(F1F4, G1G4) and outputs (X,Y and XQ,YQ). Each CLB can contain both random logic and synchronous elements. In addition to the generalpurpose logic functions, each CLB also contains special fast carry logic for addition operations. The XC4000series contains both local and global routing resources. The local resources allow extremely low delay interconnection of CLBs within the same neighborhood, as well as more extended connection through the use of switching matrices. The global resources provide for the lowdelay distribution of signals that are used at widelyspaced points in the array. The speed of a particular application is highly dependent on routing in the Xilinx FPGAs. The XC4000 family includes parts ranging from 8 by 8 CLB arrays to 24 by 24 CLB arrays. All of these devices are insystem power versions of many of these parts are also available. 3. MULTIPLYACCUMULATE UNITS Several authors [1, 11, 12, 13] have identified the multiply accumulate (MAC) operation as the kernel of various digital signal processing 重慶大學(xué)本科學(xué)生畢業(yè)設(shè)計(jì)（論文）附件 D5 algorithms. A variety of approaches to the implementation of the multiplication and addition portions of the MAC function are possible [7, 10]. This work will focus on the realization of multiplication using an array approach and addition using ripple carry methods, although other methods are equally applicable to the FPGA domain. The structure of a MAC unit is illustrated in Figure 1. The MAC unit presented in this section consists of an 8bit by 8bit binatorial array multiplier and a 16bit accumulator. These word sizes were chosen to balance the size of the implementation,which is limited by the FPGA density, against the numerical precision. Larger word sizes are possible if the number of MAC units per chips is reduced. The increase in density of FPGAs in the future will certainly expand the design space available to the designer, and make such constraints less severe. . Implementation of Multiplier The binatorial multiplier uses one CLB per partial product bit. A 2inputAND gate generates each partial product, but additional 附件 D：譯文原文 D6 circuitry is required to add together all partial products of equal weight. The total number of CLBs used for the multiplier in this case is 64 and the basic cell structure is illustrated in Figure 2. Each cell is configured as a full adder (except for the type A cell). This full adder accepts a sum and a carry from a previous operation of equal weight, as shown in Figure 2, and the logical AND of the inputs xi and ai. The sum and carry generated by the adder are then sent to the CLBs of proper weight as shown in Figure 3. The multiplier has been configured to perform multiplication of signed 重慶大學(xué)本科學(xué)生畢業(yè)設(shè)計(jì)（論文）附件 D7 numbers in two’s plement notation. The small circles in the figure indicate negative inputs or outputs。 in all the cases studied, it was practical to implement two IIR sections on a single chip. Figure 11. Placement of Two Dedicated Second Order IIR Filters on XC4013 6. PIPELINEDMAC UNITS It has been mentioned that the delay in the multiplier poses a major limitation on the maximum sampling rate that can be attained. Array multipliers can be configured to allow a pipelined mode of operation, 附件 D：譯文原文 D22 where the execution of separate multiplications overlaps. If this mode of operation is applied, the long delay associated with the carry propagating addition performed in the last row of the array multiplier can be minimized, since it determines the throughput of the pipeline. This approach has been shown to yield extremely high speed custom implementations [5]. With this more aggressive pipelining, a MAC unit which operates at rates approaching 100 MHz can be implemented on the XC4000series FPGAs, thus providing a building block for high sampling rate filters. The pipelined MAC units can be applied to high performance FIR and IIR filter structures, as well as other signal processing algorithms which can tolerate the pipeline delay. 重慶大學(xué)本科學(xué)生畢業(yè)設(shè)計(jì)（論文）附件 D23 . Structure of the Pipelined MAC Unit The structure of the pipelined MAC unit is shown in Figure basic cells shown here are identical to that in the unpipelined MAC unit except that these cells include pipeline registers. Registers are needed to propagate the multiplier and multiplicand bits to their destination and also to propagate the product bits that have been pleted, which is done in parallel w