【正文】 重慶大學(xué)本科學(xué)生畢業(yè)設(shè)計(jì)（論文）附件 D1 附件 D： FPGA IMPLEMENTATION OF DIGITAL FILTERS ChiJui Chou, Satish Mohanakrishnan, Joseph B. Evans Telemunicationsamp。 Information Sciences Laboratory Department of Electrical amp。 Computer Engineering University of Kansas Lawrence, KS 660452228 ABSTRACT Digital filtering algorithms are most monly implemented using general purpose digital signal processing chips for audio applications, or special purpose digital filtering chips and applicationspecific integrated circuits (ASICs) for higher rates. This paper describes an approach to the implementation of digital filter algorithms based on field programmable gate arrays (FPGAs).The advantages of the FPGA approach to digital filter implementation include higher sampling rates than are available from traditional DSP chips,lower costs than an ASIC for moderate volume applications, and more flexibility than the alternate approaches. Since many current FPGA architectures are insystem programmable, the configuration of the device may be changed to implement different functionality if required. Our examples illustrate that the FPGA approach is both flexible and provides performance parable or superior to traditional approaches. 1. INTRODUCTION The most mon approaches to the implementation of digital filtering algorithms are general purpose digital signal processing chips for audio applications, or special purpose digital filtering chips and applicationspecific integrated circuits (ASICs)for higher rates [9, 14]. This paper describes an approach to the implementation of digital filter algorithms on field programmable gate arrays (FPGAs).Recent advances in FPGA technology have enabled these devices to be applied to a variety of applications traditionally reserved for ASICs. FPGAs are well suited to datapath designs,such as those encountered in digital filtering applications. The density of the new programmable devices is such that a nontrivial number of arithmetic operations such as those encountered in digital filtering may be implemented on a single device. The advantages 附件 D：譯文原文 D2 of the FPGA approach to digital filter implementation include higher sampling rates than are available from traditional DSP chips, lower costs than an ASIC for moderate volume applications, and more flexibility than the alternate particular, multiple multiplyaccumulate (MAC) units may be implemented on a single FPGA, which provides parable performance to generalpurpose architectures which have a single MAC unit. Further, since many current FPGA architectures are insystem programmable, the configuration of the device may be changed to implement alternate filtering operations, such as lattice filters and gradientbased adaptive filters, or entirely different functionality. 2. BACKGROUND Research on digital filter implementation has concentrated on custom implementation using various VLSI technologies. The architecture of these filters has been largely determined by the target applications of the particular implementations. Several widely used digital signal processors such as the Texas Instruments TMS320,Motorola 56000, and Analog Devices ADSP2100 families have been designed to efficiently implement filtering operations at audio rates. These devices are extremely flexible, but are limited in performance. High performance designs for filtering at sampling rates above 100 MHz have also been demonstrated using CMOS[3, 4, 6, 8, 9, 14, 17, 19, 20, 21] and BiCMOS [8, 20, 22] technologies,using approaches ranging from full custom to traditional factoryconfigured gate arrays. These efforts have produced high performance designs for specific application domains. There are several potential shortings of the custom VLSI approach, although it does promise the best performance and efficiency for the specific application for which a particular design is intended. The most obvious problem is the lack of flexibility in the custom approach. Custom devices are often suited only for use in a particular application, and can not be easily reconfigured for other operations even within that same domain. Another Problem which the customVLSI approach often imposes is a lack of adaptability once a device is in use within a system. Typical custom approaches do not allow the function of a device to be modified within the system, for purposes such as correcting faults, for example. Although these problems can be overe with sufficient forethought, the costs in performance, implementation plexity, and 重慶大學(xué)本科學(xué)生畢業(yè)設(shè)計(jì)（論文）附件 D3 additional design time often preclude flexible solutions. Lack of flexibility can forestall the costeffective evaluation of exotic algorithms in a high performance realtime environment. Only high volume applications or extremely critical low volume applications can justify the expense of developing a full custom solution. There are a variety of algorithms which are not within the performance envelope of general purpose processors,and which are not sufficiently monplace or wellunderstood to justify implementation in a full custom design. These algorithms cannot be evaluated with the traditional approaches, thus limiting innovation. Field programmable gate arrays (FPGAs) can be used to alleviate some of the problems with the custom approach. FPGAs are programmable logic devices which bear a significant resemblance to traditional custom gate arrays. While there are a variety of approaches to FPGA implementation, some of the more popular series consist of an array of arbitrarily programmable function blocks, with configurable routing resources which are used to interconnect these blocks. Many of the most popular FPGAs are insystem programmable, which al