【正文】 acitor Cs. The original placing in the DCblocking to two directions: to the output (load) and, more important, it blocks the direct DCcurrent path through Lp to our case the blocking capacitor is underneath the resonating circuit as shown in , where the Cs obstructs the flow of DCcurrent through Lp to ground, but not to the output (load). There is a direct way for fundamental current to flow to the output, without passing any blocking capacitor. The DC blocking capacitor can now be made significantly smaller. In our case the reduction was from100 pF to less than 50 pF, which means savings in chip area and as a secondary effect, the ability to tune a stabilizing trap to wanted frequency (more in chapter ) while maintaining good amplifier performance. The design of the DCblock is now also slightly easier, since peak current flowing into the blocking branch is smaller. Furthermore,the ESR between drain and load is smaller. The fundamental current amplitudes in ponents Cs and 2 A, respectively. The total peak currents in the parallel resonator structure can be seen in . The traditional inverse class E dimensioning [4] GHz and Pout=3 W results in large chip area, as due to high Q =10 the capacitor Ctot is large ( pF) and—due to high peak currents (ca. 6 A)—the inductor gets physically huge. To get reasonable onchip ponent values the design was gradually deviated from the design procedure in [4] by shifting it towards lower load resistance and Q value, and increasing the resonance frequency. This ended up in a dimensioning that provides clean, nonoverlapping current and voltage pulses, reasonable size passives, but which is eventually closer to class C–E fundamental load [9] than to original inverse class E. The final ponent values of the simulation with discrete ponent models and an offchip lowpass impedance matching network to 50Ω resulted in the following dimensioning:resistive load 4Ω,Ctot =30 pF,Lp=0:22 nH,and L so small it could be omitted from the final could be reduced down to 50 pF without affecting the overall performance, and it can be used to tune a stabilizing below thecarrier notch, as shown later in Fig. 8. The overall simulation results with a large switching transistor (12parallel transistors with 1850181。m/ fingers) estimated W output power with 72% drain efficiency. The challenge was now to maintain as good output power and efficiency while replacing the ideal circuit ponents with process design kit (PDK) ponents and while adding some stabilizing circuits to the design problem came with the physical design of the inductor. Despite the lowered Q value the current amplitude was still so high ( A peak) that ca. 200lmwide metal line was needed for the inductor, and to keep the center of the 3/4turn inductor open it could not be made physically smaller than nH. Hence, the capacitance Ctot and Q value were further reduced a bit, and to reduce resistive losses the capacitance Ctot was split into 12parallel highQ capacitors. The drawn layout of the resonator structure was imported into field simulator, and Sparameters were simulated and pared with those of the discrete simulation prototype. The unloaded phase and magnitude of the impedance data for parisons from Sparameter simulations are shown in . The phase and magnitude data of a distributed resonator is marked with a dashed line in both figures. The phases and magnitudes of the resonators follow almost the same the plete amplifier was simulated, the drain efficiency was about 70% and output power was W. The reduction in output power may be explained by parasitic resistances and by the addition of stabilizing circuits. The drain efficiency is surprisingly good despite the somewhat lowered Q and empirical output circuit simulated and implemented distributed resonator is shown in . Stabilizing the amplifier The amplifier showed a tendency of instability during largesignal Sparameter (LSSP) simulations. In the end,stability had to be evaluated through LSSPbased stability circles since unconditional stability (K1) could not be achieved without heavy losses. Stability circles were drawn throughout a frequency range of –5 GHz. After several simulations, a variety of stabilizing circuits had to be used to pensate ringing the discrete capacitor Cs was tuned to 50 pF to generate a trap in the output resonator at about GHz frequency. This helped in achieving stability at frequencies below the frequency bandas shown by Rollett’s Kfactor in . The 50 pF value was chosen for both small degradation in output power and for good stability performance. The effect of tuning of the capacitor Cs is shown in Fig. 8, where the capacitor is tuned from 30 to 70 pF. Further, 5Ωof series resistance was added to three gate lines as shown in Fig. 9(b) to keep the amplifier stable with output standing wave ratio (SWR) range of :1. Also, a wideband RCsink circuit was included in the input of the amplifier to reduce the gain in higher stable output SWR range increased with the RC filter to :1. According to the simulations the series resistances caused about dB gain loss and the RC filter again an additional dB. If the amplifier had to be unconditionally stable (K1), in the frequency range of GHz to GHz, the increase of series resistances to 9Ω would cause an additional dB gain loss and more attenuation to the drive signal. The total decrease of gain due to stabilization would then be dB, from maximum gain of – dB. In the implemented form, the maximum simulated gain is dB. Input signal timing in a physically large transistor During simulations there was a noticeable phase shift between extreme fingers of the wide transistor consisting of12918 transistors with a width of 50lm each. This phase shift caused partial overlap between output pulses and decreased the drain efficiency. At that time the input network was made of a ladderlike structure shown as