【正文】 std_logic)。architecture Behavioral of hour1 isbegin Process(clkh,reset,set)BeginIf reset=39。 then hor2Elsif set=39。 then hor2Elsif(clkh39。139。end if。end Behavioral。use 。use 。use 。dat2,dat1 : inout std_logic_vector(3 downto 0)。end date1。139。event and clkd=39。)thenif dat2=“0011” AND dat1=“0000” then dat2else dat1end if。End process。月顯示模塊 library IEEE。use 。Unment the following lines to use the declarations that areprovided for instantiating Xilinx primitive UNISIM。entity month1 isPort(clkn,set: in std_logic。enmon : out std_logic)。architecture Behavioral of month1 isbeginProcess(clkn,set)Beginif set=39。 then mon2Elsif(clkn39。139。end if。年顯示模塊 library IEEE。use 。Unment the following lines to use the declarations that areprovided for instantiating Xilinx primitive UNISIM。entity yearth1 isPort(clkn,set: in std_logic。enyear : out std_logic)。architecture Behavioral of yearth1 isbeginProcess(clkn,set)Beginif set=39。 then year2Elsif(clkn39。139。end if。第三篇：多功能數(shù)字鐘課程設(shè)計(jì)整點(diǎn)報(bào)時(shí)與鬧鐘功能VHDL代碼library IEEE。use 。Unment the following lines to use the declarations that areprovided for instantiating Xilinx primitive UNISIM。entity timkeeper isPort(up,setpin,upclk,settime,run : in std_logic。result: out std_logic)。architecture Behavioral of timkeeper isponent h_m_s_time port（clk0,clk1,ce : in std_logic。lock : in std_logic_vector(2 downto 0)。min0,min1 : buffer std_logic_vector(3 downto 0)。ov : out std_logic)。ponent date port（clk0,clk1,ce : in std_logic。up : in std_logic。date0,date1 : buffer std_logic_vector(3 downto 0)。end ponent。lock : in std_logic_vector(2 downto 0)。mon0,mon1 : buffer std_logic_vector(3 downto 0)。end ponent。sec0,sec1,min0,min1,hour0,hour1 : in std_logic_vector(3 downto 0)。a0,a1,b0,b1,c0,c1 : out std_logic_vector(3 downto 0))。ponent alarm Port（hour1,hour0,min1,min0,sec1,sec0 : in std_logic_vector(3 downto 0)。result : out std_logic)。signal Tlock:std_logic_vector(2 downto 0)。signal Tsec0,Tsec1,Tmin0,Tmin1,Thour0,Thour1:std_logic_vector(3 downto 0)。signal Tovday,Tovmonth:std_logic。begin vccif rising_edge(setpin)thenTlockend if。u2:h_m_s_time port map(Tsecond_wave,upclk,vcc,Tsec0,Tsec1,Tlock,up，Tmin0,Tmin1,Thour0,Thour1,Tovday)。u4:month_year port map(Tovmonth,upclk,vcc,Tlock,up,Tmon0,Tmon1,Tyear0,Tyear1)。u6:alarm port map(Tsec0,Tsec1,Tmin0,Tmin1,Thour0,Thour1,settime,run ,result)。library IEEE。use 。Unment the following lines to use the declarations that areprovided for instantiating Xilinx primitive UNISIM。use 。settime,run : in std_logic。end alarm。begin p0:process(settime)beginif settime=39。thendhour1dhour0dmin1dmin0dsec1dsec0end if。p1:process(run)begin if run=39。thenif hour1=dhour1 and hour0=dhour0 and min1=dmin1 and min0=dmin0 and sec1=dsec1 and sec0 =dsec0 thenresultelse resultend if。end Behavioral。use 。use 。use 。entity date isPort(clk0,clk1,ce : in std_logic。up : in std_logic。date0,date1 : buffer std_logic_vector(3 downto 0)。end date。signal tempy1,clk:std_logic。begin tempy0beginif(lock=“000” or lock=“001”)then clkelse clkend if。u2:process(clk,ce)beginif rising_edge(clk)thenif(ce=39。)thenif(lock=“000”)or(lock=“001”)or(lock=“100” and up=39。)thenif(mon0=“0010” and mon1=“0000”)thenFeb_add_day(Td0,Td1,tempy0,tempy1,date0,date1)。else evenmonth_add_day(Td0,Td1,date0,date1)。end if。039。elsif((mon0=“0001” and mon1=“0000”)or(mon0=“0011” and mon1=“0000”)or(mon0=“0101” and mon1=“0000”)or(mon0=“0111” and mon1=“0000”)or(mon0=“1000” and mon1=“0000”)or(mon0=“0000” and mon1=“0001”)or(mon0=“0010”and mon1=“0001”))thenoddmonth_sub_day(Td0,Td1,date0,date1)。end if。end if。end process u2。139。039。139。elsif(date0=“1000” and date1=“0010”)then ovelsif((mon0=“0001” and mon1=“0000”)or(mon0=“0011” and mon1=“0000”)or(mon0=“0010” and mon1=“0000”)or(mon0=“0111” and mon1=“0000”)or(mon0=“1000” or(mon0=“0000” and mon1=“0001”)or(mon0=“0010” and mon1=“0001”))thenif(date0=“0001” and date1=“0011”)thenovelse ovend if。end if。end process u3。library IEEE。andmon1=“0000”)use 。Unment the following lines to use the declarations that areprovided for instantiating Xilinx primitive UNISIM。use 。sec0,sec1 : buffer std_logic_vector(3 downto 0)。up : in std_logic。hour0,hour1 : buffer std_logic_vector(3 downto 0)。end h_m_s_time。signal clk:std_logic。end process u1。139。139。end if。039。end if。end if。end if。end if。139。end if。039。end if。139。end if。039。end if。end if。end Behavioral。use 。use 。use 。sec0,sec1,min0,min1,hour0,hour1 : in std_logic_vector(3 downto 0)。a0,a1,b0,b1,c0,c1 : out std_logic_vector(3 downto 0))。architecture Behavioral of LED_disp is begin process(lock,sec0,sec1,min0,min1,hour0,hour1,date0,date1,mon0,mon1,year0,year1)beginif(lock=“000”)thena0end if。if(lock=“001”)thena0end if。if(lock=“110”)thena0end if。if(lock=“010”)then a0a0end if。end process。library IEEE。use 。Unment the following lines to use the declarations that areprovided for instantiating Xilinx primitive UNISIM。use 。lock : in std_logic_vector(2 downto 0)。mon0,mon1 : buffer std_logic_vector(3 downto 0)。end month_year。signal clk:std_logic。end process u1。139。139。end if。039。end if。end if。if(lock=“010” and up=39。)thenadd_year(Ty0,Ty1,year0,year1)。if(lock=“010” and up=39。)thensub_year(Ty0,Ty1,year0,year1)。end if。end process u2。library ieee。use 。signal newyear0:out std_logic_vector。procedure add_month(oldmonth0,oldmonth1:in std_logic_vector。signal newmonth1:out std_logic_vector)。signal newmonth0:out std_logic_vector。procedure sub_year(oldyear0,oldyear1:in std_logic_vector。signal newyear1:out std_logic_vector)。ty0:in std_logic_vector(1 downto 0)。signal newday0:out std_logic_vector。procedure Feb_sub_day(oldday0,oldday1:in std_logic_vector。ty1:in std_logic。signal newday1:out std_logic_vector)。signal newday0:out std_logic_vector。procedure oddmonth_sub_day(oldday0,oldday1:in std_logic_vector