【正文】 procedure oddmonth_sub_day(oldday0,oldday1:in std_logic_vector。signal newday1:out std_logic_vector)。procedure Feb_sub_day(oldday0,oldday1:in std_logic_vector。ty0:in std_logic_vector(1 downto 0)。procedure sub_year(oldyear0,oldyear1:in std_logic_vector。signal newmonth1:out std_logic_vector)。signal newyear0:out std_logic_vector。library ieee。end if。if(lock=“010” and up=39。if(lock=“010” and up=39。end if。end if。139。signal clk:std_logic。mon0,mon1 : buffer std_logic_vector(3 downto 0)。use 。use 。end process。if(lock=“110”)thena0end if。architecture Behavioral of LED_disp is begin process(lock,sec0,sec1,min0,min1,hour0,hour1,date0,date1,mon0,mon1,year0,year1)beginif(lock=“000”)thena0end if。sec0,sec1,min0,min1,hour0,hour1 : in std_logic_vector(3 downto 0)。use 。end Behavioral。end if。end if。end if。end if。end if。end if。039。139。end process u1。end h_m_s_time。up : in std_logic。use 。andmon1=“0000”)use 。end process u3。elsif(date0=“1000” and date1=“0010”)then ovelsif((mon0=“0001” and mon1=“0000”)or(mon0=“0011” and mon1=“0000”)or(mon0=“0010” and mon1=“0000”)or(mon0=“0111” and mon1=“0000”)or(mon0=“1000” or(mon0=“0000” and mon1=“0001”)or(mon0=“0010” and mon1=“0001”))thenif(date0=“0001” and date1=“0011”)thenovelse ovend if。039。end process u2。end if。039。else evenmonth_add_day(Td0,Td1,date0,date1)。)thenif(lock=“000”)or(lock=“001”)or(lock=“100” and up=39。begin tempy0beginif(lock=“000” or lock=“001”)then clkelse clkend if。end date。up : in std_logic。use 。use 。thenif hour1=dhour1 and hour0=dhour0 and min1=dmin1 and min0=dmin0 and sec1=dsec1 and sec0 =dsec0 thenresultelse resultend if。thendhour1dhour0dmin1dmin0dsec1dsec0end if。end alarm。use 。use 。u6:alarm port map(Tsec0,Tsec1,Tmin0,Tmin1,Thour0,Thour1,settime,run ,result)。u2:h_m_s_time port map(Tsecond_wave,upclk,vcc,Tsec0,Tsec1,Tlock,up，Tmin0,Tmin1,Thour0,Thour1,Tovday)。signal Tovday,Tovmonth:std_logic。signal Tlock:std_logic_vector(2 downto 0)。ponent alarm Port（hour1,hour0,min1,min0,sec1,sec0 : in std_logic_vector(3 downto 0)。sec0,sec1,min0,min1,hour0,hour1 : in std_logic_vector(3 downto 0)。mon0,mon1 : buffer std_logic_vector(3 downto 0)。end ponent。up : in std_logic。ov : out std_logic)。lock : in std_logic_vector(2 downto 0)。result: out std_logic)。Unment the following lines to use the declarations that areprovided for instantiating Xilinx primitive UNISIM。第三篇：多功能數(shù)字鐘課程設(shè)計整點(diǎn)報時與鬧鐘功能VHDL代碼library IEEE。139。architecture Behavioral of yearth1 isbeginProcess(clkn,set)Beginif set=39。entity yearth1 isPort(clkn,set: in std_logic。use 。end if。 then mon2Elsif(clkn39。enmon : out std_logic)。Unment the following lines to use the declarations that areprovided for instantiating Xilinx primitive UNISIM。月顯示模塊 library IEEE。)thenif dat2=“0011” AND dat1=“0000” then dat2else dat1end if。139。dat2,dat1 : inout std_logic_vector(3 downto 0)。use 。end Behavioral。139。 then hor2Elsif set=39。enhour : out std_logic)。Unment the following lines to use the declarations that areprovided for instantiating Xilinx primitive UNISIM。小時顯示模塊 library IEEE。)thenif min2=“0101” AND min1=“1001” then min2elsif min1=“1001” then min2else min1end if。139。end minute1。use 。use 。end if。 then sec2Elsif(clkm39。architecture Behavioral of secute1 isbeginProcess(clkm,reset,set)BeginIf reset=39。entity secute1 isPort(clkm,set,reset : in std_logic。use 。end Behavioral。begin PROCESS(ina,inb,STX)BEGIN CASE STX IS WHEN st0=r1r1r1r1r1r1r1r1STXSTXSTXSTXSTXSTXSTXSTXEND CASE。r1,r2,r3,r4,r5,r6 : out std_logic)。use 。end Behavioral。 then CASE STX IS WHEN st0=STXSTXSTXSTXSTXSTXSTXSTXEND CASE。REG2:PROCESS(clk,sel,Reset)BEGIN IF(Reset=39。architecture Behavioral of mux1 isTYPE state IS(st0,st1,st2,st3,st4,st5,st6,st7)。use 。use 。END IF。 AND clk39。REG: PROCESS(clk,Reset,sel)主控時序進(jìn)程BEGINIF Reset = 39。SIGNAL STX: states。int1,int2,int3,int4,int5,int6,int7,int8,int9,int10,int11,int12:IN STD_LOGIC_VECTOR(3 DOWNTO 0)。use 。其中reset為清0信號，當(dāng)reset為0時，星期計時器清0；set 為置數(shù)信號，當(dāng)set為0時，星期計時器置數(shù)，置y1的值，clky為驅(qū)動星期計時器工作的時鐘，與enmou相連接；year為日計時器的輸出。clkd為驅(qū)動星期計時器工作的時鐘，與enhour相連接；date為日計時器的輸出，endate為分計時器的進(jìn)位信號，作為下一級的時鐘輸入信號，由于月份的天數(shù)存在天數(shù)不同，閏年2月的天數(shù)為28天等情況，還設(shè)計了一個潤年判別器，準(zhǔn)確顯示時間。其中reset為清0信號，當(dāng)reset為0時，時計時器清0；set 為置數(shù)信號，當(dāng)set為0時，時計時器置數(shù)，置h1的值。2）分計時器（minute）是由一個60進(jìn)制的計數(shù)器構(gòu)成的，具有清0、置數(shù)和計數(shù)功能。對所有設(shè)計的小系統(tǒng)能夠正確分析；基于VHDL語言描述系統(tǒng)的功能；在quartus 2環(huán)境中編譯通過；仿真通過并得到正確的波形；給出相應(yīng)的設(shè)計報告。architecture arch of yearcounter is signal temp1,temp2:std_logic_vector(3 downto 0)。計數(shù)脈沖set: in std_logic。use 。u4:yearcounter port map(qcmonth,yearset,yearin,syear)。signal day28,day29,day30,day31:std_logic。signal dayset,monthset,yearset: std_logic。day29: out std_logic。ponent days_controlport（month: in std_logic_vector(7 downto 0)。q1: out std_logic_vector(7 downto 0)。d: in std_logic_vector(7 downto 0)。year_out: out std_logic_vector(7 downto 0))。end ponent。set: in std_logic。day30: in std_logic。day_out: out std_logic_vector(7 downto 0)。end y_m_d_count。調(diào)整位選擇data_in: in std_logic_vector(7 downto 0)。signal cp:std_logic。天脈沖clk2: in std_logic。u2:counter60 port map(qc1,reset,tsec,qc2)。end ponent。ponent counter60 port（clk: in std_logic。clr: in std_logic。秒輸出，當(dāng)超過60分轉(zhuǎn)為分min: out std_logic_vector(7 downto 0)分輸出，當(dāng)超過60分轉(zhuǎn)為小時)。then temp2temp1reset: in std_logic。end sec_mincounter。 then temp2temp1set:in std_logic。end monthcounter。計數(shù)脈沖set: in std_logic。architecture arch of hourcounter is signal temp1,temp2:std_logic_vector(3 downto 0)。調(diào)整信號d:in std_logic_vector(7 downto 0)。u3:sec_mincounter port map(qcsec,minset,minin,min,qcmin)。signal secin,minin,hourin:std_logic_vector(7 downto 0)。q2: out std_logic_vector(7 downto 0)。set1:out std_logic。end ponent。set:in std_logic。q:out std_logic_vector(7 downto 0)。end h_m_s_count。秒輸出min:out std_logic_vector(7 downto 0)。1hz脈沖set: in std_logic。end dmux。set3:out std_logic。調(diào)整信號setlap: in std_logic_vector(1 downto 0)。end displ