【正文】 Of these, data (4) advanced to the semiplace mark. Start value and super price increases set up parameters as shown in Table 3 and Table 4. Billing Module (hereinafter referred MONEY) Packaging Figure4. Table 3 installed starting price Starting price (s) DIP switches (three) 001 010 011 100 101 110 111 Table 4 super price plus set up fees Super price increases (yuan) DIP switches (2) 00 01 10 11 Module By paragraph 107 of the LED digital display module and dynamic management decoding scan showed two ponents. paragraph 107 LED decoding digital control This design is used in paragraph 107 of a total digital cathode tube, in accordance with paragraph 107, 16 and 229 the number of code table shows the correlation between When_Else With_Select or VHDL language can be used to facilitate the achievement of their decoding. Figure 2 dynamic scanning display Dynamic scanning using the human visual staying principle,if not less than 24Hz frequency scanning. Eye on the scintillating display scanning pulse of the system by providing the corresponding external scanning signal circuit design, the key lies with the EC shows that he gathers data in the timing. Therefore circuit must provide synchronous pulse signal. Eight 229 counters are used here to provide synchronization pulse,VHDL procedures as follows: CIkl_label:PROCESS (scp) BEGIN IF scp 39。 one 39。 Sound IF。 left PROCESS Data revealed by the choice of control counter, VHDL procedures as follows : Temp=counterl when count= 000 else. . . Counter4 when count= 1011 else Milel when count= 100 else. . . Mile4 when count= 111。one39。039。 Display Module (hereinafter referred SHOW) Packaging Figure 4. This module is used by the two processes, and procedures in order to implement the process, a process which triggered a second resolution process. Integrated 3 Module FBI Functional module design has been pleted, Segments II use of the graphic editor (Graphic Editor) to the functional module (. sym) link. Because there Mile module Burr, it is not directly linked to and after class. portal of the output pulse signal delay circuit, with the original signal phase and the method can remove burrs. System toplevel schematic diagram shown in Figure 4. Chip definition can be directly edited. Editor in FloorPlan pin documents or under. Pins plete definition chosen device (EPM7128SIC8415), the translation after generation. Sof that. Pofreports and documents. . Access device pins report documents the use of available resources and the use of the device. Replacement of the device make it appropriate to achieve optimal allocation of resources. The general principle is to choose the device system resources used by the devices should not exceed 80% of its resources, in excess of 90%. Power system will increase instability. From the design of this device : the importation of some note in the report, only 16 output pins with the chip resource utilization was only 51%. have greater room for expansion. Figure 4 hardware design shows The design of the CP TaxiMeter counting pulses from the wheel speed sensor (dry spring).Pulse shaping evacuation counter on the device。 rectifier system, filtering, Supply relief after a taxi。 starting to realize that every kilometer. Vehicle fee increases and the length of prefabricated parameters (such as : 3 km charge yuan, yuan / km。217。 162。 CPLD to control the output wire voice chip, sent greetings to the passengers. reminded passengers told the driver to go to the location, reported to be collecting the charges. Related topics:[1]ACEXseriesallocation[2]VerilogindevelopmentFPGA/CPLD[3]DMAandhighspeedacquisitionCPLDDataControl[5]CPLDsystemandonCPLDDigitalSynthesize[7]CPLDbasedtheSerialConfigurationtheCPLDMPC850protocollogictheCPLDmixedsystem+, 器件構成該數(shù)字系統(tǒng)的設計思想和實現(xiàn)過程 ,計費模塊,譯碼動態(tài)掃描模塊等的設計方法與技巧.關鍵詞：出租車計價器 CPLD/fpga 硬件描述語言max+plus數(shù)字系統(tǒng) 隨著電子設計自動化技術的快速發(fā)展，電子系統(tǒng)的設計技術和工具，經(jīng)歷了一場深刻的變化，出現(xiàn)了大規(guī)模的可編程邏輯器件，極大的方便了設計者。本文介紹了一種epm7128slc84 15 Altera的可編程邏輯芯片為核心，附加一定的外圍電路組成的出租車計費系統(tǒng)。不同型號其車輪的直徑各不相同，通過一個選擇開關模式作出選擇。 第2條得預置一定的公里數(shù). （ 3 ）在C變量計數(shù)器（價格調(diào)整）的累積計數(shù)， 500米計費。 （ 4 ）解碼器/動態(tài)掃描距離與成本會后動態(tài)數(shù)值譯碼數(shù)碼掃描管的驅動方式. （ 5 ） LED顯示屏，將4公里和分帳與LED顯示屏（三個整數(shù)和一個小數(shù)）.2 模塊設計出租車計價器由以下模塊構成，即模式選擇模塊，計量模塊，譯碼和動態(tài)掃描模塊，模塊化設計整個系統(tǒng)，準備先用V HDL模塊，然后頂層框圖將各功能模塊聯(lián)系起來。根據(jù)該項調(diào)查，現(xiàn)有出租車輪胎直徑大約有4種，直徑520毫米， 540毫米。使100多種不同型號分別給予出租車行的每一個脈沖，通過提供預制分頻器 ，以完成頻率系數(shù)。 預制數(shù)據(jù)控制開關安裝有兩種模式。CLA是分頻器電路，占空比通過datal （ x ）的調(diào)整分頻器，并與啟動 / 復位終端（串行復位） 。車輛模塊（以下簡稱的FP ）封裝。計程模塊是一個10個規(guī)模的，除了一個計數(shù)功能。譯碼動態(tài)掃描數(shù)值計算，將被發(fā)送到顯示模塊。因此，設計圖稿要二進制狀態(tài)跳轉，從1010跳轉至1111超過六次計數(shù)。If km (3 downto 0) = 1001 then km:=km+ 0111 : Else km:=kin+1。 圖表2Starting mileage (km) DIP switches (three) 000 001 010 011 100 101 110 111 計程模塊帶有開始 / 復位終端。 里程碑的開始和開關的關系。變量計數(shù)器變量的引入。計費模塊將減少使用非BCD，但肯定不會是一步到位。計算機用于模仿AF信號，在這里和建立一個半隨機的信號，當累計了9個多或半信號 1 ，進行累積的調(diào)整。 107段的解碼數(shù)字控制這種設計是用107段共陰極數(shù)碼管，根據(jù)第107段， 16和229的人數(shù)碼表顯示之間的相關性when_else with_select或VHDL語言，可以用來協(xié)助它們實現(xiàn)解碼。會在眼睛中留下閃爍顯示的印象。動態(tài)掃描信號的電路設計，關鍵在于，與EC信號，反映了他收集數(shù)據(jù)的時間。 8 229柜臺都是用這里提供同步脈沖， VHDL的程序如下：CIkl_label:PROCESS (scp) BEGIN IF scp 39。 one 39。 Sound IF。 left PROCESS Data revealed by the choice of control counter, VHDL procedures as follows : Temp=counterl when count= 000 else. . . Counter4 when count= 1011 else Milel when count= 100 else. . . Mile4 when count= 111。從圖樣和同步模擬可以看出上述程序，并把有關數(shù)據(jù)顯示，并產(chǎn)生一個選擇性同步信號。由于位置是固定的小數(shù)點，它可能是另一個信號柜同步控制信號DP。If (count : 101 or count= 001), then data (0) = 39。 Else data (0) = 39。 End if。因為有一英里模塊毛刺，它是沒有直接聯(lián)系的并在其后的。系統(tǒng)高層示意圖如圖4所示。管腳完整的定義是選擇性器件（ epm7128sic84 15 ）。接入設備別針報告文件，利用現(xiàn)有資源和使用該設備?？偟脑瓌t是選擇設備的系統(tǒng)資源，所用的儀器應不超過總資源的80 ％。電力系統(tǒng)將增加不穩(wěn)定因素。 本次設計的出租車計費器計數(shù)脈沖CP來自車輪轉速傳感器（干簧管），脈沖經(jīng)器件內(nèi)部整形后送計數(shù)器：動態(tài)掃描脈沖由外圍電路給出； 系統(tǒng)使用整流， 濾波， 降壓后的出租車電源供電， 由于CPLD/FPGA的驅動能力有限。提高系統(tǒng)的可靠性， 設計中在LED驅動和位驅動上分別增加了電流驅動器件ULN2803和2SC1015。use ieee。all。std_logic_arith。use ieee。all。系統(tǒng)時鐘 start:in std_logic。行駛中，中途等待停止信號 fin:in