【正文】 n as the 7400 series. The gates and flip flops were independent of one another and each had its own pins. They could be connected by offchip wiring to make a puter or anything else. These chips made a new kind of puter possible. It was called a miniputer. It was something less that a mainframe, but still very powerful, and much more affordable. Instead of having one expensive mainframe for the whole organisation, a business or a university was able to have a miniputer for each major department. Before long miniputers began to spread and bee more powerful. The world was hungry for puting power and it had been very frustrating for industry not to be able to supply it on the scale required and at a reasonable cost. Miniputers transformed the situation. The fall in the cost of puting did not start with the miniputer。 although it is not obvious, on the surface, a modern x86 processor chip contains hidden within it a RISCstyle processor with its own internal RISC coding. The ining x86 code is, after suitable massaging, converted into this internal code and handed over to the RISC processor where the critical execution is performed. In this summing up of the RISC movement, I rely heavily on the latest edition of Hennessy and Patterson’s books on puter design as my supporting authority。 the puzzle is that they did the exact opposite. Moreover, built into the design of IA64 is a feature known as predication which makes it inpatible in a major way with all other instruction sets. In particular, it needs 6 extra bits with each instruction. This upsets the traditional balance between instruction word length and information content, and it changes significantly the brief of the piler writer. In spite of having an entirely new instruction set, Intel made the puzzling claim that chips based on IA64 would be patible with earlier x86 chips. It was hard to see exactly what was meant. Chips for the latest IA64 processor, namely, the Itanium, appear to have special hardware for patibility. Even so, x86 code runs very slowly. Because of the above plications, implementation of IA64 requires a larger chip than is required for more conventional instruction sets. This in turn implies a higher cost. Such at any rate, is the received wisdom, and, as a general principle, it was repeated as such by Gordon Moore when he visited Cambridge recently to open the Betty and Gordon Moore Library. I have, however, heard it said that the matter appears differently from within Intel. This I do not understand. But I am very ready to admit that I am pletely out of my depth as regards the economics of the semiconductor industry. AMD have defined a 64 bit instruction set that is more patible with x86 and they appear to be making headway with it. The chip is not a particularly large one. Some people think that this is what Intel should have done. [Since the lecture was delivered, Intel have announced that they will market a range of chips essentially patible with those offered by AMD.] The Relentless Drive towards Smaller Transistors The scale of integration continued to increase. This was achieved by shrinking the original transistors so that more could be put on a chip. Moreover, the laws of physics were on the side of the manufacturers. The transistors also got faster, simply by getting smaller. It was therefore possible to have, at the same time, both high density and high speed. There was a further advantage. Chips are made on discs of silicon, known as wafers. Each wafer has on it a large number of individual chips, which are processed together and later separated. Since shrinkage makes it possible to get more chips on a wafer, the cost per chip goes down. Falling unit cost was important to the industry because, if the latest chips are cheaper to make as well as faster, there is no reason to go on offering the old ones, at least not indefinitely. There can thus be one product for the entire market. However, detailed cost calculations showed that, in order to maintain this advantage as shrinkage proceeded beyond a certain point, it would be necessary to move to larger wafers. The increase in the size of wafers was no small matter. Originally, wafers were one or two inches in diameter, and by 2020 they were as much as twelve inches. At first, it puzzled me that, when shrinkage presented so many other problems, the industry should make things harder for itself by going to larger wafers. I now see that reducing unit cost was just as important to the industry as increasing the number of transistors on a chip, and that this justified the additional investment in foundries and the increased risk. The degree of integration is measured by the feature size, which, for a given technology, is best defined as the half the distance between wires in the densest chips made in that technology. At the present time, production of 90 nm chips is still building up Suspension of Law In March 1997, Gordon Moore was a guest speaker at the celebrations of the centenary of the discovery of the electron held at the Cavendish Laboratory. It was during the course of his lecture that I first heard the fact that you can have silicon chips that are both fast and low in cost described as a violation of Murphy’s Sod’s law as it is usually called in the UK. Moore said that experience in other fields would lead you to expect to have to choose between speed and cost, or to promise between them. In fact, in the case of silicon chips, it is possible to have both. In a reference book available on the web, Murphy is identified as an engineer working on human acceleration tests for the US Air Force in 1949. However, we were perfectly familiar with the law in my student days, when we called it by a much more prosaic name than either of those mentioned above, namely, the Law of General Cussedne