【正文】 inning, and ultimately puter graphics was to e along. Above all, transistors began to replace vacuum tubes. This change presented a formidable challenge to the engineers of the day. They had to forget what they knew about circuits and start again. It can only be said that they measured up superbly well to the challenge and that the change could not have gone more smoothly. Soon it was found possible to put more than one transistor on the same bit of silicon, and this was the beginning of integrated circuits. As time went on, a sufficient level of integration was reached for one chip to acmodate enough transistors for a small number of gates or flip flops. This led to a range of chips known as the 7400 series. The gates and flip flops were independent of one another and each had its own pins. They could be connected by offchip wiring to make a puter or anything else. These chips made a new kind of puter possible. It was called a miniputer. It was something less that a mainframe, but still very powerful, and much more affordable. Instead of having one expensive mainframe for the whole organisation, a business or a university was able to have a miniputer for each major department. Before long miniputers began to spread and bee more powerful. The world was hungry for puting power and it had been very frustrating for industry not to be able to supply it on the scale required and at a reasonable cost. Miniputers transformed the situation. The fall in the cost of puting did not start with the miniputer。 最初實(shí)驗(yàn)用的計算機(jī)是由象我一樣有著廣博知識的人構(gòu)造的。為了讓 IEE 認(rèn)識到無線工程和快速發(fā)展的電子工程并行發(fā)展是它自己的一項(xiàng)權(quán)利，我們不得不面對一些障礙。這個變化對當(dāng)時的工程師們是個不可回避的挑戰(zhàn)。 這些芯片為制造一種新的計算機(jī)提供了可能。隨著時間的推移，人們比他們付出的金錢得到的更多。 令牌環(huán)網(wǎng)需要高可靠性，由于脈沖在令牌環(huán)中傳遞，他們必須不斷的被放大并且再生。線程不是個新概念，但是它對微機(jī)來說是從未有過的。 X86 構(gòu)架已經(jīng)占據(jù)了計算機(jī)核心指令集的主導(dǎo)地位。從許多方面來說， i860 是個卓越的芯片，但是它的軟件借口不適合在工作站上應(yīng)用。這最初主要是為了滿足通常的 64 位地址空間問題。 最新的稱為 Itaninu IA64處理器顯然需要特殊的兼容性的硬件，盡管如此，x86 編碼運(yùn)行的相 當(dāng)慢。（在這篇演講稿被提交之前， Intel 表示他們將銷售一系列本質(zhì)上與 AMD 兼容的芯片） 更小晶體管的出現(xiàn) 集成度還在不斷增加，這是通過縮小原始晶體管以致可以更容易放在一個片子上。但是我已經(jīng)作好了準(zhǔn)備，去接受這樣的事實(shí)，我已經(jīng)完全不了解半導(dǎo)體經(jīng)濟(jì)學(xué)了。特別的，每條指令它需要附加的 6 位。表面上，一片現(xiàn)代的 x86 芯片包含了隱藏實(shí)現(xiàn)的 部分，好象和實(shí)現(xiàn) RISC 指令集的芯片一樣。高級語言并沒有完全消除對機(jī)器原始編碼的的使用。 模擬仿真加快了開發(fā)進(jìn)度并且被計算機(jī)設(shè)計者廣泛采用。 1980 年， RISC 運(yùn)動改變了微機(jī)世界。在劍橋大學(xué)實(shí)驗(yàn)室力，我們構(gòu)造了 CAP，一個有令人驚奇邏輯能力的微機(jī)。 隨著微機(jī)的開始流行并且功能的完善，世界急切獲得它的計算能力但總是由于工業(yè)上不能規(guī)模供應(yīng)和它可觀的價格而受到挫折。隨著時間的推移，一個片子能夠容納的最大數(shù)量的晶體管或稍微少些的邏輯門和翻轉(zhuǎn)門集成度達(dá)到了一個最大限度。世界上的計算機(jī)數(shù)量已經(jīng)增加了許多，并且性能比以前更加可靠。 在電路的設(shè)計過程中，我們經(jīng)常陷入兩難的境地。 the puzzle is that they did the exact opposite. Moreover, built into the design of IA64 is a feature known as predication which makes it inpatible in a major way with all other instruction sets. In particular, it needs 6 extra bits with each instruction. This upsets the traditional balance between instruction word length and information content, and it changes significantly the brief of the piler writer. In spite of having an entirely new instruction set, Intel made the puzzling claim that chips based on IA64 would be patible with earlier x86 chips. It was hard to see exactly what was meant. Chips for the latest IA64 processor, namely, the Itanium, appear to have special hardware for patibility. Even so, x86 code runs very slowly. Because of the above plications, implementation of IA64 requires a larger chip than is required for more conventional instruction sets. This in turn implies a higher cost. Such at any rate, is the received wisdom, and, as a general principle, it was repeated as such by Gordon Moore when he visited Cambridge recently to open the Betty and Gordon Moore Library. I have, however, heard it said that the matter appears differently from within Intel. This I do not understand. But I am very ready to admit that I am pletely out of my depth as regards the economics of the semiconductor industry. AMD have defined a 64 bit instruction set that is more patible with x86 and they appear to be making headway with it. The chip is not a particularly large one. Some people think that this is what Intel should have done. [Since the lecture was delivered, Intel have announced that they will market a range of chips essentially patible with those offered by AMD.] The Relentless Drive towards Smaller Transistors The scale of integration continued to increase. This was achieved by shrinking the original transistors so that more could be put on a chip. Moreover, the laws of physics were on the side of the manufacturers. The transistors also got faster, simply by getting smaller. It was therefore possible to have, at the same time, both high density and high speed. There was a further advantage. Chips are made on discs of silicon, known as wafers. Each wafer has on it a large number of individual chips, which are processed together and later separated. Since shrinkage makes it possible to get more chips on a wafer, the cost per chip goes down. Falling unit cost was important to the industry because, if the latest chips are cheaper to make as well as faster, there is no reason to go on offering the old ones, at least not indefinitely. There can thus be one product for the entire market. However, detailed cost calculations showed that, in order to maintain this advantage as shrinkage proceeded beyond a certain point, it would be necessary to move to larger wafers. The increase in the size of wafers was no small matter. Originally, wafers were one or two inches in diameter, and by 2020 they were as much as twelve inches. At first, it puzzled me that, when shrinkage presented so many other problems, the industry should make things harder for itself by going to larger wafers. I now see that reducing unit cost was just as important to the industry as increasing the number of transistors on a chip, and that this justified the additional investment in foundries and the increased risk. The degree of integration is measured by the feature size, which, for a given technology, is best