【正文】 ficantly the brief of the piler writer. In spite of having an entirely new instruction set, Intel made the puzzling claim that chips based on IA64 would be patible with earlier x86 chips. It was hard to see exactly what was meant. Chips for the latest IA64 processor, namely, the Itanium, appear to have special hardware for patibility. Even so, x86 code runs very slowly. Because of the above plications, implementation of IA64 requires a larger chip than is required for more conventional instruction sets. This in turn implies a higher cost. Such at any rate, is the received wisdom, and, as a general principle, it was repeated as such by Gordon Moore when he visited Cambridge recently to open the Betty and Gordon Moore Library. I have, however, heard it said that the matter appears differently from within Intel. This I do not understand. But I am very ready to admit that I am pletely out of my depth as regards the economics of the semiconductor industry. AMD have defined a 64 bit instruction set that is more patible with x86 and they appear to be making headway with it. The chip is not a particularly large one. Some people think that this is what Intel should have done. [Since the lecture was delivered, Intel have announced that they will market a range of chips essentially patible with those offered by AMD.] The Relentless Drive towards Smaller Transistors The scale of integration continued to increase. This was achieved by shrinking the original transistors so that more could be put on a chip. Moreover, the laws of physics were on the side of the manufacturers. The transistors also got faster, simply by getting smaller. It was therefore possible to have, at the same time, both high density and high speed. There was a further advantage. Chips are made on discs of silicon, known as wafers. Each wafer has on it a large number of individual chips, which are processed together and later separated. Since shrinkage makes it possible to get more chips on a wafer, the cost per chip goes down. Falling unit cost was important to the industry because, if the latest chips are cheaper to make as well as faster, there is no reason to go on offering the old ones, at least not indefinitely. There can thus be one product for the entire market. However, detailed cost calculations showed that, in order to maintain this advantage as shrinkage proceeded beyond a certain point, it would be necessary to move to larger wafers. The increase in the size of wafers was no small matter. Originally, wafers were one or two inches in diameter, and by 2020 they were as much as twelve inches. At first, it puzzled me that, when shrinkage presented so many other problems, the industry should make things harder for itself by going to larger wafers. I now see that reducing unit cost was just as important to the industry as increasing the number of transistors on a chip, and that this justified the additional investment in foundries and the increased risk. The degree of integration is measured by the feature size, which, for a given technology, is best defined as the half the distance between wires in the densest chips made in that technology. At the present time, production of 90 nm chips is still building up Suspension of Law In March 1997, Gordon Moore was a guest speaker at the celebrations of the centenary of the discovery of the electron held at the Cavendish Laboratory. It was during the course of his lecture that I first heard the fact that you can have silicon chips that are both fast and low in cost described as a violation of Murphy’s Sod’s law as it is usually called in the UK. Moore said that experience in other fields would lead you to expect to have to choose between speed and cost, or to promise between them. In fact, in the case of silicon chips, it is possible to have both. In a reference book available on the web, Murphy is identified as an engineer working on human acceleration tests for the US Air Force in 1949. However, we were perfectly familiar with the law in my student days, when we called it by a much more prosaic name than either of those mentioned above, namely, the Law of General Cussedness. We even had a mock examination question in which the law featured. It was the type of question in which the first part asks for a definition of some law or principle and the second part contains a problem to be solved with the aid of it. In our case the first part was to define the Law of General Cussedness and the second was the problem。世界上的計(jì)算機(jī)數(shù)量已經(jīng)增加了許多，并且性能比以前更加可靠。 隨著微機(jī)的開始流行并且功能的完善，世界急切獲得它的計(jì)算能力但總是由于工業(yè)上不能規(guī)模供應(yīng)和它可觀的價(jià)格而受到挫折。 1980 年， RISC 運(yùn)動(dòng)改變了微機(jī)世界。高級(jí)語(yǔ)言并沒有完全消除對(duì)機(jī)器原始編碼的的使用。特別的，每條指令它需要附加的 6 位。（在這篇演講稿被提交之前， Intel 表示他們將銷售一系列本質(zhì)上與 AMD 兼容的芯片） 更小晶體管的出現(xiàn) 集成度還在不斷增加，這是通過縮小原始晶體管以致可以更容易放在一個(gè)片子上。這最初主要是為了滿足通常的 64 位地址空間問題。 X86 構(gòu)架已經(jīng)占據(jù)了計(jì)算機(jī)核心指令集的主導(dǎo)地位。 令牌環(huán)網(wǎng)需要高可靠性，由于脈沖在令牌環(huán)中傳遞，他們必須不斷的被放大并且再生。 這些芯片為制造一種新的計(jì)算機(jī)提供了可能。為了讓 IEE 認(rèn)識(shí)到無(wú)線工程和快速發(fā)展的電子工程并行發(fā)展是它自己的一項(xiàng)權(quán)利，我們不得不面對(duì)一些障礙。 what would cause a harmless flash on the screen of a television set could lead to a serious error in a puter. As far as puting circuits were concerned, we found ourselves with an embarass de richess. For example, we could use vacuum tube diodes for gates as we did in the EDSAC or pentodes with control signals on both grids, a system widely used elsewhere. This sort of choice persisted and the term families of logic came into use. Those who have worked in the puter field will remember TTL, ECL and CMOS. Of these, CMOS has now bee dominant. In those early years, the IEE was still dominated by power engineering and we had to fight a number of major battles in order to get radio engineering along with the rapidly developing subject of in the IEE light current electrical recognised as an activity in its own right. I remember that we had some difficulty in organising a conference becaus