【正文】 n designers of mercially available machines added additional features which they thought would improve performance. Few parative measurements were done and on the whole the choice of features depended upon the designer’s intuition. In 1980, the RISC movement that was to change all this broke on the world. The movement opened with a paper by Patterson and Ditzel entitled The Case for the Reduced Instructions Set Computer. Apart from leading to a striking acronym, this title conveys little of the insights into instruction set design which went with the RISC movement, in particular the way it facilitated pipelining, a system whereby several instructions may be in different stages of execution within the processor at the same time. Pipelining was not new, but it was new for small puters The RISC movement benefited greatly from methods which had recently bee available for estimating the performance to be expected from a puter design without actually implementing it. I refer to the use of a powerful existing puter to simulate the new design. By the use of simulation, RISC advocates were able to predict with some confidence that a good RISC design would be able to outperform the best conventional puters using the same circuit technology. This prediction was ultimately born out in practice. Simulation made rapid progress and soon came into universal use by puter designers. In consequence, puter design has bee more of a science and less of an art. Today, designers expect to have a roomful of, puters available to do their simulations, not just one. They refer to such a roomful by the attractive name of puter farm. The x86 Instruction Set Little is now heard of preRISC instruction sets with one major exception, namely that of the Intel 8086 and its progeny, collectively referred to as x86. This has bee the dominant instruction set and the RISC instruction sets that originally had a considerable measure of success are having to put up a hard fight for survival. This dominance of x86 disappoints people like myself who e from the research academic and the puter field. No doubt, business considerations have a lot to do with the survival of x86, but there are other reasons as well. However much we research oriented people would like to think otherwise. high level languages have not yet eliminated the use of machine code altogether. We need to keep reminding ourselves that there is much to be said for strict binary patibility with previous usage when that can be attained. Nevertheless, things might have been different if Intel’s major attempt to produce a good RISC chip had been more successful. I am referring to the i860 (not the i960, which was something different). In many ways the i860 was an excellent chip, but its software interface did not fit it to be used in a workstation. There is an interesting sting in the tail of this apparently easy triumph of the x86 instruction set. It proved impossible to match the steadily increasing speed of RISC processors by direct implementation of the x86 instruction set as had been done in the past. Instead, designers took a leaf out of the RISC book。 although it is not obvious, on the surface, a modern x86 processor chip contains hidden within it a RISCstyle processor with its own internal RISC coding. The ining x86 code is, after suitable massaging, converted into this internal code and handed over to the RISC processor where the critical execution is performed. In this summing up of the RISC movement, I rely heavily on the latest edition of Hennessy and Patterson’s books on puter design as my supporting authority。 see in particular Computer Architecture, third edition, 2020, pp 146, 1514, 1578. The IA64 instruction set. Some time ago, Intel and HewlettPackard introduced the IA64 instruction set. This was primarily intended to meet a generally recognised need for a 64 bit address space. In this, it followed the lead of the designers of the MIPS R4000 and Alpha. However one would have thought that Intel would have stressed patibility with the x86。 the puzzle is that they did the exact opposite. Moreover, built into the design of IA64 is a feature known as predication which makes it inpatible in a major way with all other instruction sets. In particular, it needs 6 extra bits with each instruction. This upsets the traditional balance between instruction word length and information content, and it changes significantly the brief of the piler writer. In spite of having an entirely new instruction set, Intel made the puzzling claim that chips based on IA64 would be patible with earlier x86 chips. It was hard to see exactly what was meant. Chips for the latest IA64 processor, namely, the Itanium, appear to have special hardware for patibility. Even so, x86 code runs very slowly. Because of the above plications, implementation of IA64 requires a larger chip than is required for more conventional instruction sets. This in turn implies a higher cost. Such at any rate, is the received wisdom, and, as a general principle, it was repeated as such by Gordon Moore when he visited Cambridge recently to open the Betty and Gordon Moore Library. I have, however, heard it said that the matter appears differently from within Intel. This I do not understand. But I am very ready to admit that I am pletely out of my depth as regards the economics of the semiconductor industry. AMD have defined a 64 bit instruction set that is more patible with x86 and they appear to be making headway with it. The chip is not a particularly large one. Some people think that this is what Intel should have done. [Since the lecture was delivered, Intel have announced that they will market a range of chips essentially patible with those offered by AMD.] The Relentless Drive towards Smaller Transistors The scale of integra