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基于fpga出租車計(jì)價(jià)器設(shè)計(jì)-展示頁

2024-11-29 21:56本頁面
  

【正文】 n, the principle is clear, fast, strong function, high reliability, strong flexibility, and plete and additional functional extension. This design has realized the taxi meter required some basic functions, such as log, timing, pricing, dynamic display, billing amount fare and mileage charging, waiting for the timing. Through the Quartus II Software Platform, using Verilog HDL language pleted the description and simulation of frequency module, the meter module, Billing module, timing modules, decoding, dynamic scanning display module,for each module are simulated respectively and toplevel module with schematic design , the simulation waveform were analyzed. After download validation hardware, pleted the taxi meter divider module, log module, billing module, timing module, decoding and dynamic scanning display modules designed to achieve. Keywords: FPGA; Taximeter; Quartus II; Verilog HDL 目 錄 1 前言 ................................................................................................................................. 1 課題的來源及意義 ................................................................................................. 1 國內(nèi)外發(fā)展?fàn)顩r ...................................................................................................... 1 研究的手段及目標(biāo) ................................................................................................. 2 2 總體方案設(shè)計(jì) ............................................................................................................. 3 方案論證與選擇 ...................................................................................................... 3 設(shè)計(jì)思想及原理 ...................................................................................................... 4 3 FPGA、 Verilog 及 QuartusⅡ開發(fā)環(huán)境的介紹 ......................................... 6 現(xiàn)場可編程門陣列 FPGA ....................................................................................... 6 硬件描述語言 Verilog HDL ................................................................................ 6 QuartusⅡ開發(fā)環(huán)境 ............................................................................................... 7 4 設(shè)計(jì)與仿真驗(yàn)證 ........................................................................................................ 8 分頻模塊 .................................................................................................................... 8 計(jì) 程分頻模塊 ...................................................................................................... 8 計(jì)時(shí)分頻模塊和計(jì)費(fèi)分頻模塊 ..................................................................... 9 數(shù)碼管動(dòng)態(tài)顯示模塊 ........................................................................................ 9 數(shù)碼管動(dòng)態(tài)顯示模塊 仿真 ............................................................................... 9 計(jì)程模塊 .................................................................................................................. 10 計(jì)程 模塊電路 .................................................................................................... 10 計(jì)程模塊仿真 .................................................................................................... 12 計(jì)時(shí)模塊 .................................................................................................................. 12 計(jì)時(shí)模塊電路 .................................................................................................... 12 計(jì)時(shí)模塊仿真 .................................................................................................... 13 計(jì)費(fèi)模塊 .................................................................................................................. 14 計(jì)費(fèi)模塊電路 .................................................................................................... 14 計(jì)費(fèi)模塊仿真 .................................................................................................... 15 數(shù)碼管顯示模塊 .................................................................................................... 16 數(shù)碼管顯示模塊電路 ...................................................................................... 16 數(shù)碼管顯示仿真 ............................................................................................... 17 整體頂層模塊設(shè)計(jì)電路 ...................................................................................... 17 下載實(shí)現(xiàn) .................................................................................................................. 20 5 結(jié)論 ............................................................................................................................... 23 參考文獻(xiàn) ............................................................................................................................ 24 致謝 ...................................................................................................................................... 24 附錄 ...................................................................................................................................... 25 1 1 前言 課題的來源及意義 本課題是在老師指導(dǎo)下,根據(jù)學(xué)校教學(xué)的需求和實(shí)際需要而開發(fā)的研究項(xiàng) 目。該設(shè)計(jì)采用模塊化設(shè)計(jì),自頂向下,在 Quartus ,采用 Verilog HDL 硬件描述語言分別設(shè)計(jì)了分頻模塊、 計(jì)程模塊 、 計(jì)費(fèi)模塊 、計(jì)時(shí)模塊, 譯碼 以及 動(dòng)態(tài)掃描 顯示 模塊 的
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