【正文】 ulses to the output. These pulses are phase shifted and therefore do not overlap with each other. Ideal nonoverlap causes the transistor to operate with drain efficiency of 100%. Classical class E drain waveforms, normalized to DC values of supply current and voltage, are shown in solid line is normalized drain current waveform and the dashed line is normalized drain voltage. The requirement for optimal operation in class E is zero voltage switching (ZVS), where the drain voltage and its derivative goes to zero just before the transistor starts to conduct. In inverse class E the waveforms have swapped places so that the solid line waveform in is the drain voltage and the dashed line is the drain current. The optimal operation is also changed to zerocurrent switching (ZCS), where the current and its derivative goes smoothly to zero before the transistor enters nonconducting phase. Advantages of inverse class E over classical realization are that the drain peak voltages are lower than in classical class E and the inductance values in the output circuitry are smaller, which can save area in a MMIC chip implementation and can usually give smaller electrical series resistance (ESR) [4]. Also, the possibility to acmondate series inductance as a part of resonating circuitry is useful, since the parasitic reactances can cause undamped resonances to drain waveforms [6, 7]. These advantages were the reasons for choosing inverse class E topology as a starting point for our investigation. However, the tuned implementation is not traditional inverse class E, although it has similar pulsed operation. 3 Design of tuned power amplifier GaAs IC processThe IC process used is a Triquint Semiconductor’s pseudomorphic high electron mobility transistor (pHEMT) process named TQPED. The process utilizes both enhancement and depletion mode field effect transistors (FETs) with length optical lithography gates, but in our case we used only depletion mode transistors. The available depletion mode transistors have a transition frequency (Ft) of 27 GHz, draingate breakdown voltage of15 V and nominal pinchoff point V. Transistors models used are TOM3 FET models. There are several other features in the process: nichrome (NiCr) resistors for precision and bulk for high value resistors, high value Metal–Insulator–Metal (MIM) capacitors, 1 local and 2thick global metal layers [8]. Design of the resonator The difference between the original inverse class E in the final tuned topology used in our design,shown in , is the location of blocking capacitor Cs. The original placing in the DCblocking to two directions: to the output (load) and, more important, it blocks the direct DCcurrent path through Lp to our case the blocking capacitor is underneath the resonating circuit as shown in , where the Cs obstructs the flow of DCcurrent through Lp to ground, but not to the output (load). There is a direct way for fundamental current to flow to the output, without passing any blocking capacitor. The DC blocking capacitor can now be made significantly smaller. In our case the reduction was from100 pF to less than 50 pF, which means savings in chip area and as a secondary effect, the ability to tune a stabilizing trap to wanted frequency (more in chapter ) while maintaining good amplifier performance. The design of the DCblock is now also slightly easier, since peak current flowing into the blocking branch is smaller. Furthermore,the ESR between drain and load is smaller. The fundamental current amplitudes in ponents Cs and 2 A, respectively. The total peak currents in the parallel resonator structure can be seen in . The traditional inverse class E dimensioning [4] GHz and Pout=3 W results in large chip area, as due to high Q =10 the capacitor Ctot is large ( pF) and—due to high peak currents (ca. 6 A)—the inductor gets physically huge. To get reasonable onchip ponent values the design was gradually deviated from the design procedure in [4] by shifting it towards lower load resistance and Q value, and increasing the resonance frequency. This ended up in a dimensioning that provides clean, nonoverlapping current and voltage pulses, reasonable size passives, but which is eventually closer to class C–E fundamental load [9] than to original inverse class E. The final ponent values of the simulation with discrete ponent models and an offchip lowpass impedance matching network to 50Ω resulted in the following dimensioning:resistive load 4Ω,Ctot =30 pF,Lp=0:22 nH,and L so small it could be omitted from the final could be reduced down to 50 pF without affecting the overall performance, and it can be used to tune a stabilizing below thecarrier notch, as shown later in Fig. 8. The overall simulation results with a large switching transistor (12parallel transistors with 1850181。m/ fingers) estimated W output power with 72% drain efficiency. The challenge was now to maintain as good output power and efficiency while replacing the ideal circuit ponents with process design kit (PDK) ponents and while adding some stabilizing circuits to the design problem came with the physical design of the inductor. Despite the lowered Q value the current amplitude was still so high ( A peak) that ca. 200lmwide metal line was needed for the inductor, and to keep the center of the 3/4turn inductor open it could not be made physically smaller than nH. Hence, the capacitance Ctot and Q value were further reduced a bit, and to reduce resistive losses the capacitance Ctot was split into 12parallel highQ capacitors. The drawn layout of the resonator structure was imported into field simulator, and Sparameters were simulated and pared with those of the discrete simulation prototype. The unloaded phase and magnitude of the impedance data for parisons from Sparameter simulations are shown in . The phase and magnitude data of a distributed resonator is marked wi