【正文】 an be used as highimpedance 0 may also be configured to be the multiplexed loworder address/data busduring accesses to external program and data memory. In this mode P0 has 0 also receives the code bytes during Flash programming,and outputs the codebytes during program verification. External pullups are required during programverification.Port 1：Port 1 is an 8bit bidirectional I/O port with internal Port 1 output buffers can sink/so urce four TTL 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal 1 also receives the loworder address bytes during Flash programming and verification.Port 2：Port 2 is an 8bit bidirectional I/O port with internal Port 2 outputbuffers can sink/source four TTL 1s are written to Port 2 pins they arepulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 2 emits the highorder address byte during fetches from external program memory and during accesses to Port 2 pins that are externally being pulled low will source current (IIL) because of the internal 2 emits the highorder address byte during fetches from external program memory and during accesses to external data memory that use 16bit addresses (MOVXDPTR). In this application, it uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8bit addresses (MOVX RI), Port 2 emits the contents of the P2 Special Function 2 also receives the highorder address bits and some control signals durin Flash programming and verification.Port 3：Port 3 is an 8bit bidirectional I/O port with internal Port 3 outputbuffers can sink/sou rce four TTL 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of various special featuresof the AT89C51 as listed below:RST：Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/PROG：Address Latch Enable output pulse for latching the low byte of the address duringaccesses to external pin is also the program pulse input (PROG) during Flash normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency,and may be used for external timing or clocking purposes. Note, however, that one ALEpulse is skipped duri ng each access to external desired, ALE operationcan be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active onlyduring a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Settingthe ALEdisable bit has no effect if the microcontroller is in external execution mode.PSEN：Program Store Enable is the read strobe to external program memory. When theAT89C51 is executing code from external program memory, PSEN is activated twiceeach machine cycle, except that two PSEN activations are skipped during each access toexternal data memory.EA/VPP：External Access Enable. EA must be strapped to GND in order to enable the deviceto fetch code from external program memory locations starting at 0000H up to , however, that if lock bit 1 is programmed, EA will be internally latched should be strapped to VCC for internal program executions. This pin alsreceives the 12volt programming enable voltage (VPP) during Flash programming, forparts that require 12volt VPP.XTAL1：Input to the inverting oscillator amplifier and input to the internal clock operatingcircuit. XTAL2 ：Output from the inverting oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifierwhich can be configured for use as an onchip oscillator, as shown in Figure 1. Either aquartz crystal or ceramic resonator may be used. To drive the device from an externalclock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a dividebytwo flipflop, but minimum and maximum voltage high and low time specifications must be observed. Idle Mode In idle mode, the CPU put