基于單片機(jī)的智能晾衣架控制系統(tǒng)的設(shè)計(jì)與實(shí)現(xiàn)外文文獻(xiàn)原稿和譯文-展示頁
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【正文】 erAUXR Address=8EH Reset Value=XXX00XX0b Not Bit Addressable– –– WDIDLE DISRTO–– DISALEBit 7 6 5 4 3 2 1 0 Reserved for future expansionDISALE Disable/Enable ALE DISALE Operating Mode 0 ALE is emitted at a constant rate of 1/6 the oscillator frequency 1 ALE is active only during a MOVX or MOVC instruction DISRTO Disable/Enable Resetout DISRTO 0 Reset pin is driven High after WDT times out 1 Reset pin is input only WDIDLE Disable/Enable WDT in IDLE modeWDIDLE0 WDT continues to count in IDLE mode 1 WDT halts counting in IDLE mode Dual Data Pointer Registers: To facilitate accessing both internal and external data memory, two banks of 16bit Data Pointer Registers are provided: DP0 at SFR address locations 82H83H and DP1 at 84H85H. Bit DPS = 0 in SFR AUXR1 selects DP0 and DPS = 1 selects DP1. The user should always initialize the DPS bit to the appropriate value before accessing the respective Data Pointer Register.Power Off Flag: The Power Off Flag (POF) is located at bit 4 () in the PCON SFR. POF is set to “1” during power up. It can be set and rest under software control and is not affected by reset.4 Memory OrganizationMCS51 devices have a separate address space for Program and Data Memory. Up to 64K bytes each of external Program and Data Memory can be addressed. Program MemoryIf the EA pin is connected to GND, all program fetches are directed to external memory. On the AT89S51, if EA is connected to VCC, program fetches to addresses 0000H through FFFH are directed to internal memory and fetches to addresses 1000H through FFFFH are directed to external memory. Data MemoryThe AT89S51 implements 128 bytes of onchip RAM. The 128 bytes are accessible via direct and indirect addressing modes. Stack operations are examples of indirect addressing, so the 128 bytes of data RAM are available as stack space.5 Watchdog Timer (Onetime Enabled with Resetout) The WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets. The WDT consists of a 14bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, it will increment every machine cycle while the oscillator is running. The WDT timeout period is dependent on the external clock frequency. There is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH pulse at the RST pin. Using the WDTTo enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, the user needs to service it by writing 01EH and 0E1H to WDTRST to avoid a WDT overflow. The 14bit counter overflows when it reaches 16383 (3FFFH), and this will reset the device. When the WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 16383 machine cycles. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a writeonly register. The WDT counter cannot be read or written. When WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET pulse duration is 98xTOSC, where TOSC = 1/FOSC. To make the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset. WDT DURING Powerdown and IdleIn Powerdown mode the oscillator stops, which means the WDT also stops. While in Powerdown mode, the user does not need to service the WDT. There are two methods of exiting Powerdown mode: by a hardware reset or via a levelactivated external interrupt, which is enabled prior to entering Powerdown mode. When Powerdown is exited wi
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