【正文】 9 掉電模式 在掉線模式下，振蕩器停止工作，進(jìn)入掉電模式的指令是最后一條被執(zhí)行的指令，片內(nèi)RAM和特殊功能寄存器的內(nèi)容在終止掉電模式前被凍結(jié)。如圖71所示。當(dāng)WDIDLE位被置位，在空閑模式中看門狗定時器將停止計數(shù)，直到從空閑(IDLE)模式中退出重新開始計數(shù)。掉電模式下，用戶不嗯那個在復(fù)位看門狗定時器。外部復(fù)位時，看門狗定時器（WDT）默認(rèn)為關(guān)閉狀態(tài)，要打開WDT，用戶必須按順序?qū)?1EH和0E1H寫到WDTRST寄存器（SFR地址為0A6H），當(dāng)啟動了WDT，它會隨警惕振蕩器在每個機(jī)器周期計數(shù)，除了硬件復(fù)位或WDT溢出復(fù)位外沒有其它方法關(guān)閉WDT，當(dāng)WDT溢出，將使RST引腳輸出高電平的復(fù)位脈沖。用戶應(yīng)在訪問相應(yīng)的數(shù)據(jù)指針寄存器前初始化DPS位。P3端口可以采用AT89S51的各種特殊功能，如下表所示。當(dāng)作輸入口使用時，因?yàn)閮?nèi)部存在上拉電阻，某個引腳被外部信號拉低時會輸出一個電流（IIL）。在Flash編程時，PO端口接收指令字節(jié)，而在程序校驗(yàn)時，輸出指令字節(jié)，同時要求外接上拉電阻。此外， AT89S51設(shè)計了可降至零頻率的靜態(tài)邏輯操作和支持兩種軟件可選的節(jié)電工作模式。芯片上的Flash程序存儲器在系統(tǒng)中可重新編程或常規(guī)非易失性內(nèi)存編程 。對端口寫“1”可作為高阻抗輸入端用。端口引腳 第二功能MOSI(用于ISP編程)MISO（用于ISP編程）SCK(用于ISP編程) P2端口是一個帶有內(nèi)部上拉電阻的8位雙向I/O端口。P3端口輸出緩沖級可驅(qū)動（吸收或輸出電流）4個TTL邏輯門電路。 中斷寄存器：各個中斷控制位于IE寄存器，5個中斷源的中斷優(yōu)先級控制位于IP寄存器。 數(shù)據(jù)存儲器 AT89S51具有128字節(jié)的內(nèi)部RAM 。復(fù)位脈沖持續(xù)時間為98xTosc，而Tosc=1/Fosc(晶體振蕩頻率)。為保證看門狗定時器在退出掉電模式時極端情況下不溢出，最好在進(jìn)入掉電模式前復(fù)位看門狗定時器。，用戶不要訪問這些位，它是保留為以后的AT89產(chǎn)品擴(kuò)展用途。此時，片內(nèi)RAM和所有特殊功能寄存器的內(nèi)特那個保持不變，空閑模式可由任何語序中斷的請求或硬件復(fù)位終止。表91 空閑和掉電期間外部引腳狀態(tài)模式程序存儲區(qū)ALEPSENPORT0PORT1PORT2PORT3空閑模式內(nèi)部11數(shù)據(jù)數(shù)據(jù)數(shù)據(jù)數(shù)據(jù)空閑模式外部11浮空數(shù)據(jù)地址數(shù)據(jù)掉電模式內(nèi)部00數(shù)據(jù)數(shù)據(jù)數(shù)據(jù)數(shù)據(jù)掉電模式外部00浮空數(shù)據(jù)數(shù)據(jù)數(shù)據(jù)10。由于外部時鐘信號是通過一個2分頻觸發(fā)器后作為內(nèi)部時鐘信號的，所以對外部時鐘信號的占空比沒有特殊要求，但是最小高電平持續(xù)時間和最大的低電平時序時間應(yīng)符合產(chǎn)品技術(shù)條件的要求。這些中斷源各自的禁止和使能位參見特殊功能寄存器的IE。以防止中斷誤復(fù)位，當(dāng)器件復(fù)位，中斷引腳持續(xù)為低時，看門狗定時器并未開始計數(shù)，知道中斷引腳被拉高時為止。WDT打開時，它會隨著晶體振蕩器在每個機(jī)器周期計數(shù)，這意味著用戶必須在小于每個16383機(jī)器周期內(nèi)復(fù)位WDT，也即寫01EH和0E1H到WDTRST寄存器，WDTRST為只寫寄存器。 程序存儲器 如果的EA引腳接地（GND），全部程序都可以執(zhí)行外部存儲器。而寫這些地址單元不能得到預(yù)期的結(jié)果。Flash編程或校驗(yàn)時，P2也可接收高位地址和其它控制信號。對端口寫“1”，通過內(nèi)部的上拉電阻把端口拉到高電平，此時可作為輸入口。 2 端口P0端口是一個8位漏極開路雙向I / O端口。燕京理工學(xué)院畢業(yè)設(shè)計（論文）——外文文獻(xiàn)原稿和譯文外文文獻(xiàn)原稿和譯文原　　稿The Description of AT89S511 General DescriptionThe AT89S51 is a lowpower, highperformance CMOS 8bit microcontroller with 4K bytes of InSystem Programmable Flash memory. The device is manufactured using Atmel’s highdensity nonvolatile memory technology and is patible with the industrystandard 80C51 instruction set and pinout. The onchip Flash allows the program memory to be reprogrammed insystem or by a conventional nonvolatile memory programmer. By bining a versatile 8bit CPU with InSystem Programmable Flash on a monolithic chip, the Atmel AT89S51 is a powerful microcontroller which provides a highlyflexible and costeffective solution to many embedded control applications.The AT89S51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, two 16bit timer/counters, a fivevector twolevel interrupt architecture, a full duplex serial port, onchip oscillator, and clock circuitry. In addition, the AT89S51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Powerdown mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next external interrupt or hardware reset.2 PortsPort 0 is an 8bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance inputs. Port 0 can also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode, P0 has internal pullups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pullups are required during program verification.Port 1 is an 8bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 1 also receives the loworder address bytes during Flash programming and verification.Port PinAlternate FunctionsMOSI (used for InSystem Programming)MOSO (used for InSystem Programming) SCK(used for InSystem Pro