基于單片機(jī)的智能晾衣架控制系統(tǒng)的設(shè)計(jì)與實(shí)現(xiàn)外文文獻(xiàn)原稿和譯文-文庫(kù)吧
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【正文】 external input)WR(external data memory write strobe)RD(external data memory read strobe)3 Special Function RegistersA map of the onchip memory area called the Special Function Register (SFR) space is shown in Table 31. Table 31. AT89S51 SFR Map and Reset Values0F8H 0FFH 0F0H B 00000000 0F7H 0E8H 0EFH 0E0H ACC 00000000 0E7H 0D8H 0DFH 0D0H PSW 00000000 0D7H 0C8H 0CFH 0C0H 0C7H 0B8H IP XX000000 0BFH 0B0H P3 11111111 0B7H 0A8H IE 0X000000 0AFH 0A0H P2 11111111 AUXR1 XXXXXXX0 WDTRST XXXXXXXX 0A7H 98H SCON 00000000 SBUF XXXXXXXX 9FH 90H P1 11111111 97H 88H TCON 00000000 TMOD 00000000 TL0 00000000 TL1 00000000 TH0 00000000 TH1 00000000 AUXR XXX00XX 8FH 80H P0 11111111 SP 00000111 DP0L 00000000 DP0H 00000000 DP1L 00000000 DP1H 00000000 PCON 0XXX0000 87H Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0. Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the five interrupt sources in the IP register.Table 32. AUXR:Auxiliary RegisterAUXR Address=8EH Reset Value=XXX00XX0b Not Bit Addressable– –– WDIDLE DISRTO–– DISALEBit 7 6 5 4 3 2 1 0 Reserved for future expansionDISALE Disable/Enable ALE DISALE Operating Mode 0 ALE is emitted at a constant rate of 1/6 the oscillator frequency 1 ALE is active only during a MOVX or MOVC instruction DISRTO Disable/Enable Resetout DISRTO 0 Reset pin is driven High after WDT times out 1 Reset pin is input only WDIDLE Disable/Enable WDT in IDLE modeWDIDLE0 WDT continues to count in IDLE mode 1 WDT halts counting in IDLE mode Dual Data Pointer Registers: To facilitate accessing both internal and external data memory, two banks of 16bit Data Pointer Registers are provided: DP0 at SFR address locations 82H83H and DP1 at 84H85H. Bit DPS = 0 in SFR AUXR1 selects DP0 and DPS = 1 selects DP1. The user should always initialize the DPS bit to the appropriate value before accessing the respective Data Pointer Register.Power Off Flag: The Power Off Flag (POF) is located at bit 4 () in the PCON SFR. POF is set to “1” during power up. It can be set and rest under software control and is not affected by reset.4 Memory OrganizationMCS51 devices have a separate address space for Program and Data Memory. Up to 64K bytes each of external Program and Data Memory can be addressed. Program MemoryIf the EA pin is connected to GND, all program fetches are directed to external memory. On the AT89S51, if EA is connected to VCC, program fetches to addresses 0000H through FFFH are directed to internal memory and fetches to addresses 1000H through FFFFH are directed to external memory. Data MemoryThe AT89S51 implements 128 bytes of onchip RAM. The 128 bytes are accessible via direct and indirect addressing modes. Stack operations are examples of indirect addressing, so the 128 bytes of data RAM are available as stack space.5 Watchdog Timer (Onetime Enabled with Resetout) The WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets. The WDT consists of a 14bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT i
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