【正文】 obtain the best circuit performance. All power rails to the analog ICs should be thick, and decoupled to ground with capacitors physically close to the devices: at least 1uF (tantalum) in parallel with 100nF (ceramic). A good ground plane should be included, especially around the MAX471, because high frequency, high amplitude currents occupy that territory. The resistors on the MAX471 should be precision types with low inductance, because any tolerance on these ponents directly affects the results. All analog PCB tracks should be as short as possible and far away from digital lines. The MAX125 reference amplifier should be decoupled at input and output, close to the IC. Ideally, the board should incorporate separate analog and digital ground planes, connected at a single point. It was observed that the 10MHz clock appears in unexpected places, so if this signal is to be routed across the pc board it should be physically remote from analog inputs, especially the resistor works and with a ground track in between. To further minimize noise radiation, this signal can be filtered to remove clock harmonics and reconstituted using a simple digital gate placed close to the processor and ADC. A 39。s serial clock line (SCLK) must start in the LOW state when CS is asserted. If this requirement presents a problem, you should cycle the SCLK line before entering the SPI routine. Note the time required for RS232 data to transmit. At 9600 baud, it takes more than one millisecond to transmit eight bits of data together with the start and stop bits. This is obvious in hindsight, but it can give the designer hours of undeserved enjoyment not only in wondering why data is not reaching the PC correctly, but also in illustrating the difference in operating speeds of the microprocessor and the RS232 link. A simple 10ms delay inserted in the code allows data transmission and processing at the PC end. Note also that the RS232 spec does not detail the signal protocol (start and stop bits, etc.)。C es and goes so fast (in 1181。s mode of operation to receive inputs from all four channels of MUX A. Once this is established, the microprocessor ports are reconfigured as inputs to receive data from the ADC. When CONVST is pulsed low, the processor waits for an interrupt signal from the MAX125. It then reads out the conversion of channel 1 and sends the result (via the MAX3100 UART and the MAX202E) to the PC39。C for a 12 bit system, and 30ppm/176。C, divide by the reference voltage and multiply by 106. The result is normally about 2ppm/176。C. Next, decide on the maximum drift (in volts) that can be tolerated (normally 1/2 to 1 LSB) over the temperature range, and hence the drift in V/176。C) needed for any digitisation system is straightforward. First, define the system39。s input code changes, the input impedance of the reference input also changes, thereby modulating the reference voltage. Fortunately, the MAX12539。s theorem) are described in many papers and books. An antialiasing filter removes these unwanted frequencies. The effect of aliasing can be quite subtle if you consider the frequency spectrum of any signal that is not purely sinusoidal. A nonsinewave by definition has harmonics, and these higher harmonics translate downward to cause errors at the lower frequencies. Again, unless the input signal frequency range is definitely known, a bination buffer and antialiasing filter is always good design practice. Minimal filtering is required because the system in question takes only spot readings. For higher sampling frequencies, a simple lowpass filter using ponents C1, C2, C3, and C4 provides signal rolloff ahead of the ADC input. These ponents also serve to average out the readings taken by the ADC, and they effectively remove ripple from the input and output power measurements. Digitization The MAX125 is a selfcontained, simultaneoussampling, successiveapproximation dataacquisition system with onchip RAM. It samples two sets of four signals using 2x4 sample/hold amplifiers, which are then digitized sequentially by a single ADC block. The results are stored in RAM and read out sequentially on the parallel data bus under processor control. The MAX125 also includes a voltage reference whose spuriousfree dynamic range (SFDR) is suitable for many highresolution DSP applications. (The internal reference can be overridden by an external system reference.) The MAX125 also exhibits good INL (the maximum deviation of real from theoretical ADC output), good DNL (the deviation of real from theoretical ADC step magnitude) and monotonicity to 13 bits (an output code that increases or remains unchanged in response to an increasing analog input). To enable efficient use of the microprocessor, the MAX125 provides a pushpull interrupt output indicating when the conversion has finished. An internal buffer allows use of either the internal or an external reference. As for the analog input, the reference input should be driven from a lowimpedance source. This applies especially for ADCs that employ a successiveapproximation register (SA