【正文】 rpose. A number of factors should be considered to obtain absolute dc accuracy. The MAX873A reference offers excellent drift specifications, for example, but its initial accuracy (177。s internal buffer eliminates this concern. For this design, the internal reference was overridden by an external, precision, lowdropout, lowdrift voltage reference (MAX873A). Although its use (vs. the internal reference) provided no noticable change in results, the MAX873A offers better initial accuracy and drift. Gaining an idea of the drift specification (in ppm/176。s theorem) are described in many papers and books. An antialiasing filter removes these unwanted frequencies. The effect of aliasing can be quite subtle if you consider the frequency spectrum of any signal that is not purely sinusoidal. A nonsinewave by definition has harmonics, and these higher harmonics translate downward to cause errors at the lower frequencies. Again, unless the input signal frequency range is definitely known, a bination buffer and antialiasing filter is always good design practice. Minimal filtering is required because the system in question takes only spot readings. For higher sampling frequencies, a simple lowpass filter using ponents C1, C2, C3, and C4 provides signal rolloff ahead of the ADC input. These ponents also serve to average out the readings taken by the ADC, and they effectively remove ripple from the input and output power measurements. Digitization The MAX125 is a selfcontained, simultaneoussampling, successiveapproximation dataacquisition system with onchip RAM. It samples two sets of four signals using 2x4 sample/hold amplifiers, which are then digitized sequentially by a single ADC block. The results are stored in RAM and read out sequentially on the parallel data bus under processor control. The MAX125 also includes a voltage reference whose spuriousfree dynamic range (SFDR) is suitable for many highresolution DSP applications. (The internal reference can be overridden by an external system reference.) The MAX125 also exhibits good INL (the maximum deviation of real from theoretical ADC output), good DNL (the deviation of real from theoretical ADC step magnitude) and monotonicity to 13 bits (an output code that increases or remains unchanged in response to an increasing analog input). To enable efficient use of the microprocessor, the MAX125 provides a pushpull interrupt output indicating when the conversion has finished. An internal buffer allows use of either the internal or an external reference. As for the analog input, the reference input should be driven from a lowimpedance source. This applies especially for ADCs that employ a successiveapproximation register (SAR), because the reference voltage feeds directly into the DAC39。s serial clock line (SCLK) must start in the LOW state when CS is asserted. If this requirement presents a problem, you should cycle the SCLK line before entering the SPI routine. Note the time required for RS232 data to transmit. At 9600 baud, it takes more than one millisecond to transmit eight bits of data together with the start and stop bits. This is obvious in hindsight, but it can give the designer hours of undeserved enjoyment not only in wondering why data is not reaching the PC correctly, but also in illustrating the difference in operating speeds of the microprocessor and the RS232 link. A simple 10ms delay inserted in the code allows data transmission and processing at the PC end. Note also that the RS232 spec does not detail the signal protocol (start and stop bits, etc.)。 在啟動或 電源 復(fù)位 時 , max125 配置采用雙向數(shù)據(jù) 管腳 D3D0 . 將這些管腳置 0， 1 ，并置 WR 為低就將 ADC 置于操作模式，以接收 四路 MUX 輸入信號。 結(jié)果 , 該裝置 max1705在試驗 ( DUT )下 ,DCDC升壓轉(zhuǎn)換器設(shè)定在 PWM 模式 . 負(fù)載應(yīng)用到評價工具， 其結(jié)果采取凍結(jié) max125 PC 程序和閱讀價值 ,從屏幕 . 然后用 (已廢棄 )數(shù)字萬用表 證實 結(jié)果 , 并與預(yù)期效益所作圖的數(shù)據(jù) 相比較 : 表 1 . Load/ Vin/V Iin/A Vout/V Iout/A Efficiency/% (exp. Eff/%) 95 50 92 100 83 390 56 校正 ， 錯誤和 tweaks 雖然數(shù)字可能 會有不同 , 模擬 部分 布局必須是無可挑剔的 ,以取得最佳 的電路性能 . 所有電源線路的模擬集成電路應(yīng)厚 ，并且 與電容器封閉 不相干的地面的裝置 : 至少 1uf (鉭 )平行 100nf (陶瓷 ) . 良好的 電路板 應(yīng)包括在內(nèi) ,特別是在 MAX471 附近 ,因為高頻高幅值電流占據(jù) 這里 . max471 的 電阻 應(yīng) 是 精密型 ,低電感 因為任何 元件的誤差 直接影響的結(jié)果 . 所有模擬 PCB 的軌跡應(yīng)盡可能短 ,并遠(yuǎn)離數(shù)字線路 . MAX125 的參考放大器必須在不相干的 輸 入與 輸 出 ,靠近集成電路 . 理想的情況下 ,板子 應(yīng)納入單獨的模擬和數(shù)字地面機 ,連接在一個點 . 據(jù) 觀察 10mhz 時鐘出現(xiàn)在意想 不到的地方 , 因此 ,如果這一信號是 跨過 PCB板， 必須從模擬 輸入 , 尤其是電阻網(wǎng)絡(luò)與 板子 軌道之間 . 為了進(jìn)一步減少噪音輻射 ， 這一信號可以歸納為消除時鐘諧波和重組 ,用一個簡單的數(shù)字閘門靠近了 處理器和 ADC . 可以很好地達(dá)到這一目的。 較高的采樣頻率 ,一個簡單的低通濾波器元件 在 ADC輸入之前用器件 c1 , c2 , c3 , 與C4提供 信號 rolloff. 這些成分還有助于平均出 ADC讀數(shù) , 并 從輸入和輸出功率的測量 有效消除紋波 . Digitization max125 的是自足 ,同步采樣 ,連續(xù)數(shù)逼近數(shù)據(jù)采集系統(tǒng)的存儲器芯片 . 它 用2x4采樣 /保持放大器 采樣 兩 個系列 四個信號 ， 然后 用單獨的一個 ADC 模塊 按順序 數(shù)字 化 . 結(jié)果存放在 RAM并且 在處理器控制 下由 并行數(shù)據(jù)總線 按 順序 讀出 . max125 的還包括一個參考電壓 ， 雜散自由動態(tài)范圍 ( SFDR 指標(biāo) )是適合多種高分辨率 DSP應(yīng)用 . (外 部參考可以推翻一個 內(nèi) 部系統(tǒng)參考 ) . max125 的 能，inl (理論上 ADC 輸出 的最大偏差 )性能 好 ， dnl (理論上 ADC 步幅的真正偏差 )也不錯， 和單 獨 13 bits (輸出代碼 增加或保持不變就增加模擬輸入 ) . 為使有效使用的微處理器 , max125 提供了推拉中斷輸出 ,說明當(dāng)轉(zhuǎn)換完畢 . 一個內(nèi)部的緩沖允許利用任何內(nèi)部或外部參考 . 至于模擬輸入 ,參考輸入應(yīng) 從低阻抗源 拿出 . 這特別適用作 ADCS， 用逐次逼近 寄存器 (SAR) , 因為參考電壓直接 進(jìn) 入 DAC 的 R2R 階梯 . 由于 DAC 的輸入代碼更改 ,阻抗參考輸入的變化 ,從而調(diào)節(jié)參