【正文】 PC計數(shù)器在 第一 時間 復(fù)位 。這 樣 一旦確立 , 微處理器 部分 重新接收來自 ADC的數(shù)據(jù)。 為 了解 低源阻抗 究竟要有多低，需 考慮一個簡單的數(shù)學(xué)計算的RC時間常數(shù) . 輸入 電容 大小依據(jù)： vcap = vin (1et/CR), , 其中 C是 取樣電容器 ， R為抗源 ,Vin 是 RC電路 中的應(yīng)用 電壓 . 不同電壓之間vin和 vcap之間在電壓上的不同 是 : vin vcap = vin et/CR 因此 ,已給取樣值 和 hold 電容器 (一般為 10 30pf ) ,電容器 的 充電時間 與誤差電壓是可 接受 的 ( 1 / 2 lsb ) 可以計算最大允許信號源電阻 ,將 在 一定時間內(nèi)給 電容器 充電 . 輸入緩沖還可以作為一種過濾器清除不必要的信號 . 因為 ADC 是一種取樣系統(tǒng) ,其輸出光譜具有對稱性偏 約一半的采樣頻率 . 因此 ,信號大于一半的采樣頻率 和 不到一半的采樣頻率 無法區(qū)分信號 . 以 10khz 采樣頻率 為 例 ， ADC 是無法區(qū)分一個 4khz 和 6khz 的輸 入 , 因為 均 是對稱的大約一半的采樣頻率( 5khz ) . 盡管本條適用范圍 有太多規(guī)定 , 這一效應(yīng) (混 )和定理 ,說明它 (奈奎斯特定理 )描述了許多論文和書籍 . 反走樣過濾器 刪除這些無 用的頻率 . 如果 認(rèn)為該頻譜的任何信號并不是純正弦波 .效果走樣可以相當(dāng)微妙 , 一個非正弦波的定義諧波 ,這些高次諧波將向下造成誤差在較低的頻率 . 另外 ,除非輸入信號頻率范圍是 完全 已知 ， 結(jié)合緩沖 的反鋸齒過濾總是好的設(shè)計實踐 . 由于出現(xiàn)問題的系統(tǒng) 只 能 spot readings， 最小過濾是需要的 。 just the voltage levels, slew rate, and connector details. The MAX3100 and MAX202E, however, handle all the standards for making data pliant with RS232, and in a protocol expected by the PC. The Windows Interface The Windows program was written in Visual Basic Version 6. It takes readings from the RS232 port using the MSComm function, configured to accept text, and converts this data to ASCII. It also translates each 16bit data block back to the voltage and current measurements obtained from analogsensing circuitry that precedes the ADC input. From these results, the input power, output power, and efficiency are calculated and displayed on the PC screen, rounded to three decimal places. In addition, the system can freeze the results if they need to be logged. The measured efficiency figures were far from consistent. This was accounted for by noticing ripple on the current and voltage waveforms. The resistors were bypassed with 10nF capacitors to reduce the currentripple readings, but the resistivedivider works measuring voltage were left unbypassed. Thus, the measured ripple (20mV on the input and 100mV on the output) accounted for the 177。C for a 14 bit system, 10ppm/176。s R2R ladder. As the DAC39。APPLICATION NOTE 1138 Practical Data Acquisition using a Windows1based Power Meter Abstract: This application note describes the design of a PCbased, 14bit data acquisition system. It takes a system approach, includes all the necessary building blocks: analog, digital, hardware, and software. It discusses each step, testing systems separately before integrating them, and detailing pitfalls learned along the way. Many articles have been written about the building blocks in a typical data acquisition system, but few address the entire system, from analog input to PC display. To cover all the problems encountered in designing a plete data acquisition system, the engineer might have to amass ten articles. The following application note describes the design of a PCbased, 14bit data acquisition system. It takes a system approach, includes all the necessary building blocks: analog, digital, hardware, and software. It discusses each step, testing systems separately before integrating them, and detailing pitfalls learned along the way. The Design Specification The task: Design a power meter based on a 14bit simultaneoussampling ADC with onchip RAM (MAX125). The need for a power meter is apparent to anyone who has tried measuring the input and output characteristics of a DCDC converter using conventional instruments. The design allows users to perform load measurements on the device under test without connecting an endless spaghettimass of test leads. Figure 1 shows the pleted power meter display on a personal puter (PC) monitor. Figure 1. Windows PC output with example readout. To cater for boost, buck, and linear implementations, the measurement range was chosen as 30V for both input and output. Most quality DCDC converters operate at 100kHz or higher. The system39。s input code changes, the input impedance of the reference input also changes, thereby modulating the reference voltage. Fortunately, the MAX12539。C for a 12 bit system, and 30ppm/176。3% vari ation in efficiency measurements. As results are read into the PC, missing data produces incorrect readings on the PC screen. The time intervals between arriving packets of data were therefore measured. If any interval exceeded seconds, the PC counter was reset in anticipation of the first character in the subsequent data packet. Results The device under test (DUT) was the MAX1705, a boost DCDC converter configured in PWM mode. Loads were applied to the evaluation kit, and the results taken by freezing the MAX125 PC program and reading values from the screen. The results were then confirmed using the (now obsolete) digital multimeter, and pared with the expected efficiency as given by graphs in the datasheet: Table 1. Load/ Vin/V Iin/A Vout/V Iout/A Efficiency/% (exp. Eff/%) 95 50 92 100 83 390 56 Calibration, Errors and Tweaks Though digital purists may argue differently, the analog board layout must be impeccable to obtain the best circuit performance. All power rails to the analog ICs should be thick, and decoupled to ground with capacitors