【正文】 tware. The content of the onchip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. Onchip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. Status of External Pins During Idle and Power Down Modes: mode Program memory ALE ^psen Port0 Port1 Port2 Port3 idle internal 1 1 data data data Data Idle External 1 1 float Data data Data Power down Internal 0 0 Data Data Data Data Power down External 0 0 float data Data data Power Down Mode: In the power down mode the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The onchip RAM and Special Function Registers retain their values until the power down mode is terminated. The only exit from power down is a hardware reset. Reset redefines the SFRs but does not change the onchip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. Program Memory Lock Bits: On the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below: Lock Bit Protection Modes When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly. Programming the Flash: The at89s52 is normally shipped with the onchip Flash memory array in the erased state (that is, contents = FFH) and ready to be programmed. The programming interface accepts either a highvoltage (12volt) or a lowvoltage (VCC) program enable signal. The low voltage programming mode provides a convenient way to program the at89s52 inside the user’s system, while the highvoltage programming mode is patible with conventional third party Flash or EPROM programmers. The at89s52 is shipped with either the highvoltage or lowvoltage programming mode enabled. The respective topside marking and device signature codes are listed in the following table. Vpp=12v Vpp=5v Topside mark at89s52 xxxx yyww at89s52 xxxx5 yyww signature (030H)=1EH (031H)=51H (032H)=FFH (030H)=1EH (031H)=51H (032H)=05H The at89s52 code memory array is programmed bytebybyte in either programming mode. To program any nonblank byte in the onchip Flash Programmable and Erasable Read Only Memory, the entire memory must be erased using the Chip Erase Mode. Programming Algorithm: Before programming the at89s52, the address, data and control signals should be set up according to the Flash programming mode table and Figures 3 and 4. To program the at89s52, take the following steps. 1. Input the desired memory location on the address lines. 2. Input the appropriate data byte on the data lines. 3. Activate the correct bination of control signals. 4. Raise EA/VPP to 12V for the highvoltage programming mode. 5. Pulse ALE/PROG