外文翻譯--at89s52單片機-wenkub
2022-11-13 08:06:51 本頁面
【正文】 are externally being pulled low will source current ( IIL )because of the internal pullups. In addition, and can be configured to be the timer/counter 2 external count input() and the timer/counter 2 trigger input (), respectively, as shown in the following table. Port 1 also receives the loworder address bytes during Flash programming and verification. Port Pin Alternate Function T2(external count input to Timer／ Counter2)，clockout T2EX(Time／ Counter2 capture／ reload trigger and direction control) ALE/ PROG : Address Latch Enable is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG ) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALEdisable bit has no effect if the microcontroller is in external execution mode. XTAL2: Output from the inverting oscillator amplifier. Oscillator Characteristics: XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an onchip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a dividebytwo flipflop, but minimum and maximum voltage high and low time specifications must be observed. Idle Mode: In idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the onchip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. Onchip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. Status of External Pins During Idle and Power Down Modes: mode Program memory ALE ^psen Port0 Port1 Port2 Port3 idle internal 1 1 data data data Data Idle External 1 1 float Data data Data Power down Internal 0 0 Data Data Data Data Power down External 0 0 float data Data data Power Down Mode: In the power down mode the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The onchip RAM and Special Function Registers retain their values until the power down mode is terminated. The only exit from power down is a hardware reset. Reset redefines the SFRs but does not change the onchip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. Program Memory Lock Bits: On the chip are three lock bits which can be left unprogrammed (U) or ca
公司管理相關(guān)推薦
鄂ICP備17016276號-1