【正文】 in parallel with R3. STEP 11. . . GAIN ADJUST Turn OFF all bits, adjust 50 W gain trimmer to give a reading of – volts. Please note that it is not necessary to trim the op amp to obtain full accuracy at room temperature. In most bipolar situations, the op amp trimmer is unnecessary unless the untrimmed offset drift of the op amp is excessive. 177。1 LSB. The AD509 is remended for buffered voltageoutput applications that require a settling time to 177。1/10 LSB (plus op amp offset), and full scale accuracy will be within 177。C, add % (100 3 ppm/176。C could, under worst case conditions for a temperature change of +25176。C and over the temperature range of interest. Differential nonlinearity is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. For example, for a 10 volt full scale output, a change of 1 LSB in digital input code should result in a mV change in the analog output (1 LSB = 10 V 180。 connecting VCC to the digital logic supply automatically sets the threshold to the proper level for the logic family being used. Logic sink current requirement is only 25 mA. 3. The high speed current steering switches are designed to settle in less than 250 ns for the worst case digital code transition. This allows construction of successiveapproximation A/D converters in the 3 ms to 5 ms range. 4. The AD561 has an output voltage pliance range from –2 V to +10 V, allowing direct currenttovoltage conversion with just an output resistor, omitting the op amp. The 40 MW open collector output impedance results in negligible errors due to output leakage currents. 5. The AD561 is available in versions pliant with MILSTD883. Refer to the Analog Devices Military Products Databook or current AD561/883B data sheet for detailed specifications. 【 2】【 Analysis and Application of AD561】 THE AD561 OFFERS TRUE 10BIT RESOLUTION OVER FULL TEMPERATURE RANGE Accuracy: Analog Devices defines accuracy as the maximum deviation of the actual, adjusted DAC output (see page 5) from the ideal analog output (a straight line drawn from 0 to FS – lLSB) for any bit bination. The AD561 is laser trimmed to 1/4 LSB (% of FS) maximum error at +25176。C to +125176。C to +70176。C max for the S, and 80 ppm/176。 the TC is tested and guaranteed to 30 ppm/176。1/4 LSB max for the K and T versions, and 1/2 LSB max for the J and S versions. 【 AD561 PRODUCT DESCRIPTION】 The AD561 also incorporates a low noise, high stability subsurface zener diode to produce a reference voltage with excellent long term stability and temperature cycle characteristics, which challenge the best discrete Zener references. A temperature pensation circuit is lasertrimmed to allow custom correction of the temperature coefficient of each device. This results in a typical fullscale temperature coefficient of 15 ppm/176。 圖 附件 2：外文原文 Introduction and Application of AD561 CHIP The AD561 is an integrated circuit 10bit digitaltoanalog converter bined with a high stability voltage reference fabricated on a single monolithic chip. Using ten precision highspeed currentsteering switches, a control amplifier, voltage reference, and lasertrimmed thinfilm SiCr resistor work, the device produces a fast, accurate analog output trimmed output application resistors are also included to facilitate accurate, stable currenttovoltage conversion。 未提交位輸入線將承擔(dān)起一個“ 1“狀態(tài)（類似于為 TTL），但他們是高阻抗和受雜音。對于大多數(shù)應(yīng)用程序，連接到 VCC 的正邏輯供應(yīng)量將在適當(dāng)?shù)募墑e設(shè)置的閾值最大噪聲免疫力。邏輯輸入負(fù)荷因子（ 100 nA 的 最大邏輯“ 1”，在邏輯 25 mA 最大 “ 0” 3 pF 的 電容），低于一數(shù)字相當(dāng)于所有負(fù)載邏輯的家庭，包括無緩沖的 CMOS。 數(shù)字邏輯接口 所有標(biāo)準(zhǔn)的接口，積極提供邏輯很容易與在 AD561。 整個轉(zhuǎn)換單元進(jìn)行相同的電流是否位或關(guān)閉時，盡