基于dsp的函數(shù)信號發(fā)生器與數(shù)據(jù)采集系統(tǒng)課程設(shè)計(完整版)(參考版)
2024-08-21 16:30本頁面
【正文】 mask the LSBnopnopnopnopstlmB, McBSP1_DXR1nopnopnopnopCALL IfRxRDY1ldm McBSP1_DRR1,bstl b,*ar2+nopnopnopnopbanzloop,*ar3nopnopretnopnop *********************wait: stm 20h,ar3loop1: stm 020h,ar4loop2:banz loop2,*ar4banz loop1,*ar3ret nopnopnopnop.end************************************************************************** End of File –– *********************************************************************。 disable McBSP0 RXLDM McBSP1_SPSD,AAND 0xFFFE, ASTLM A, McBSP1_SPSDSTM SPCR2, McBSP1_SPSA 。STM 0208h, McBSP1_DXR1 。STM 0x0001, McBSP1_DXR1。enable digital loopback 。CALL IfTxRDY1。CALL IfTxRDY1。bypass internal DPLL。request secondary municationCALL IfTxRDY1 STM 0490h, McBSP1_DXR1。request secondary municationCALL IfTxRDY1 STM 0300h, McBSP1_DXR1。request secondary municationCALL IfTxRDY1 STM 0200h, McBSP1_DXR1。request secondary municationNOPCALL IfTxRDY1 STM 0100h, McBSP1_DXR1。 NOP。STM 0x0208, McBSP1_DXR1。STM 0x0101, McBSP1_DXR1。 load data page 0rpt 23NOP ssbx xfNOPNOP。 enable McBSP0 RX for ADC data inLDM McBSP1_SPSD,AOR 0x0001, ASTLM A, McBSP1_SPSDSTM SPCR2, McBSP1_SPSA 。 keep checking NOPNOPRET 。 enable McBSP1 TxLDM McBSP1_SPSD, AAND 0002h, A 。 keep checkingNOPNOPRET 。 enable McBSP1 RxLDM McBSP1_SPSD, AAND 0002h, A 。 clear the intrupts’ flagsRET 。 FS at pulse–mode(00)******* Finish DSP Initialization *******STM 0x0000, IMR 。 register subaddress of PCRSTM 000eh, McBSP1_SPSD 。 register subaddr of XCR2STM 0040h, McBSP1_SPSD 。 register subaddr of XCR1STM 0040h, McBSP1_SPSD 。 recv Phase = 1。 recv frame1 Dlength = 16 bitsSTM RCR2, McBSP1_SPSA 。 to run after SW breakpointSTM RCR1, McBSP1_SPSA 。 XINT generated by frame syncSTM 0000h, McBSP1_SPSD 。 RINT generated by frame syncSTM SPCR2, McBSP1_SPSA 。 register subaddr of SPCR1STM 0000h, McBSP1_SPSD 。 =40M/2500=16KHz* STM 6249, PRD 。STM 2499, PRD 。 stop on–chip timer1。 OVLY=1, vectors at 0080h******* Set up Timer Control Registers *******STM 0x0010, TCR 。 ST1 at default setting(note:INTX=1)STM 0x00A0,PMST 。 ST0 at default setting。 consecutive prog/data read。 set wait states for bank switch:。 0 wait cycle for dataamp。 2 wait cycle for IO space amp。 set C5402 DSP cl
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鄂ICP備17016276號-1