【正文】 7. ONCHIP FLASH MEMORY SYSTEMThe LPC2114/2212 incorporate a 128 kB Flash memory system, while LPC2124/2214 incorporate a 256 kB Flash memory system. This memory may be used for both code and data storage. Programming of the Flash memory may be acplished in several ways: over the serial builtin JTAG interface, using In System Programming (ISP) and UART0, or by means of In Application Programming (IAP) capabilities. The application program, using the In Application Programming (IAP) functions, may also erase and/or program the Flash while the application is running, allowing a great degree of flexibility for data storage field firmware upgrades, etc.8. ONCHIP STATIC RAMThe LPC2114/2124/2212/2214 provide a 16 kB static RAM memory that may be used for code and/or data storage. The SRAMsupports 8bit, 16bit, and 32bit accesses.The SRAM controller incorporates a writeback buffer in order to prevent CPU stalls during backtoback writes. The writeback buffer always holds the last data sent by software to the SRAM. This data is only written to the SRAM when another write is requested by software (the data is only written to the SRAM when software does another write). If a chip reset occurs, actual SRAM contents will not reflect the most recent write request (. after a warm chip reset, the SRAM does not reflect the last write operation). Any software that checks SRAM contents after reset must take this into account. Two identical writes to a location guarantee that the data will be present after a Reset. Alternatively, a dummy write operation before entering idle or powerdown mode will similarly guarantee that the last data written will be present in SRAM after a subsequen Reset.9. LPC2114/2124/2212/2214 REGISTERSAccesses to registers in LPC2114/2124/2212/2214 is restricted in the following ways:1) user must NOT attempt to access any register locations not defined.2) Access to any defined register locations must be strictly for the functions for the registers.3) Register bits labeled ’’, ’0’ or ’1’ can ONLY be written and read as follows: ’’ MUST be written with ’0’, but can return any value when read (even if it was written with ’0’). It is a reserved bit and maybe used in future derivatives. ’0’ MUST be written with ’0’, and will return a ’0’ when read. ’1’ MUST be written with ’1’, and will return a ’1’ when read.10. PULSE WIDTH MODULATOR (PWM)LPC2114/2124/2212/2214 Pulse Width Modulator is based on standard Timer 0/1 described in previous chapter. Application can choose among PWM and match functions available .FEATURES? Seven match registers allow up to 6 single edge controlled or 3 double edge controlled PWM outputs, or a mix of both types.The match registers also allow: Continuous operation with optional interrupt generation on match. Stop timer on match with optional interrupt generation. Reset timer on match with optional interrupt generation.Figure 1: LPC2114/2124/2212/2214 Block Diagram? An external output for each match register with the following capabilities: Set low on match. Set high on match. Toggle on match. Do nothing on match.? Supports single edge controlled and/or double edge controlled PWM outputs. Single edge controlled PWM outputs all go high at the beginning of each cycle unless the output is a constant low. Double edge controlled PWM outputs can have either edge occur at any position within a cycle. This allows for both positive going and negative going pulses.? Pulse period and width can be any number of timer counts. This allows plete flexibility in the tradeoff between resolution and repetition rate. All PWM outputs will occur at the same repetition rate.? Double edge controlled PWM outputs can be programmed to be either positive going or negative going pulses.? Match register updates are synchronized with pulse outputs to prevent generation of erroneous pulses. Software must release。北京：冶金工業(yè)出版社；157159。[6]徐春山。ARM嵌入式處理器結(jié)構(gòu)與應(yīng)用基礎(chǔ)[M]。ARM嵌入式系統(tǒng)基礎(chǔ)教程[M]。模擬電子技術(shù)基礎(chǔ)[M]?，F(xiàn)代電力電子電路[M]。電力電子學(xué)[M]。 感謝我的爸爸媽媽，焉得諼草，言樹之背，養(yǎng)育之恩，無以回報(bào)，你們永遠(yuǎn)健康快樂是我最大的心愿。但愿進(jìn)京的國華平平安安，留守科大的子雨和大飛快快樂樂，揮師南下的小霞、小段、小常順順利利，也愿和我一起進(jìn)軍華北平原的郭郭開開心心。四年了，仿佛就在昨天。他們細(xì)心指導(dǎo)我的學(xué)習(xí)與研究，在此，我要向諸位老師深深地鞠上一躬。汪老師開朗的個(gè)性和寬容的態(tài)度，幫助我能夠很快的融入我們這個(gè)團(tuán)隊(duì)。汪老師一絲不茍的作風(fēng)，嚴(yán)謹(jǐn)求實(shí)的態(tài)度，踏踏實(shí)實(shí)的精神，不僅授我以文，而且教我做人，雖僅僅厲時(shí)三月，卻給以終生受益無窮之道。致謝本課題在選題及研究過程中得到汪玉坤老師的悉心指導(dǎo)。可以在輸出端利用電流互感器搭一個(gè)檢測(cè)回路，送給單片機(jī)的一個(gè)管腳，一旦超過上限下限就報(bào)警，使IGBT關(guān)斷，達(dá)到保護(hù)負(fù)載的作用。在硬件方面，缺少電流上下限報(bào)警。這樣可以簡(jiǎn)化軟件的設(shè)計(jì)，但又缺少了設(shè)定值的顯示。在設(shè)計(jì)中，采用的是數(shù)字輸入方式，即鍵盤輸入，還可以采用模擬輸入方式。 }while(key_exit)。 //恢復(fù)小數(shù)點(diǎn)的位置 break。 //數(shù)字變字符 get_segm(led_buf)。 if(keytemp9)keytemp=0。 case _updn : //設(shè)定某位的數(shù)字，數(shù)字范圍0~9 keytemp=toint(led_buf[i])。=0x7f。}//去掉最右位小數(shù)點(diǎn) led_buf_segm[i]|=0x80。=0x7f。 i++。 break。39。 case _back : key_exit=0。flag_send=1。 //查段碼 do{ keytemp=get_key()。 key_exit=1。 return(keyval)。 //鍵釋放,返回鍵值 keyval=keyvalamp。)。0x00fe0000。0x00fe0000。 if(!key_hit())return(0)。 //無鍵按下，返回0 return((bit)1)。0x00fe0000。 //無鍵按下，返回0 delay(10000)。0x00fe0000。 }}檢測(cè)是否有鍵按下bit key_hit(void){ BYTE keyvalue。pos++) { led_buf_segm[i]= get_strokes(*pos)。 for(pos=p。根據(jù)顯示緩沖區(qū)的內(nèi)容查段碼表填充顯示緩沖區(qū)段碼表 入口：顯示緩沖區(qū)的內(nèi)容 出口：無void get_segm(uchar* p){ uchar *pos。939。839。739。639。539。439。339。239。139。039。 uchar stroke。進(jìn)入設(shè)定狀態(tài)后，判斷哪個(gè)鍵按下，就相應(yīng)地執(zhí)行哪個(gè)鍵的功能，最后判斷是1鍵按下還是4鍵按下，若是1鍵按下存盤后退出鍵盤設(shè)定，若為4鍵則顯直接退出鍵盤設(shè)定。1鍵設(shè)定完成，存盤并退出設(shè)定狀態(tài)；4鍵，退出設(shè)定狀態(tài)，不保留設(shè)定的值；2鍵是位設(shè)定；3鍵是調(diào)數(shù)鍵，調(diào)09之間的任意的一個(gè)數(shù)。鍵盤設(shè)置了四個(gè)按鍵，有設(shè)定完成鍵，退出鍵，調(diào)位鍵和調(diào)數(shù)鍵。 } 鍵盤與顯示顯示設(shè)置了四個(gè)LED數(shù)碼管。 outputv=ui。 ui_1=ui。 //積分分離，防止積分飽和 if((setvinputv)delta) ui=ui_1+(float)propor*(erri_inc+(float)differe/time*erri_incc)。 // 變比例系數(shù)，抑制超調(diào) if((setvinputv)=0) propor*=5。 erri_1inc=err_0[1]err_0[2]。