【正文】 *CAPCONB = 0xe000。 *T4CON = 0x1870。 if(index_pwm=num_f_d)index_pwm=0。 *CMPR3=pwm_half_per*sin_table[(index_pwm+((num_f_d)/3))%(num_f_d)]。 /* *CMPR1=pwm_half_per*sin_table[index_pwm%(num_f_d)]。 b=*CMPR2=b_time*pwm_half_per*(+*sin_table[(index_pwm+((2*num_f_d)/3))%num_f_d])。 0x0001。 asm( CLRC INTM)。 } i++。 基于 DSP 的三相異步電機(jī)控制 34 b_time=fv_/((float)*T2PR)。 *ADCTRL2|=0x4200。 if(adc_res0x3fe)adc_res=0x3fe。 */ if(!(i%I_DIV)) { adc_res=*RESULT56。 Speed_result[i] = T4_NUM1 T4_NUM0。 } void interrupt adcint(void) { asm( clrc SXM)。 *CHSELSEQ2=0x7654。 *MAX_CONV=0x07。 /* enable desired EVB group C interrupts */ } void init_adc(void) { *ADCTRL1=0x00。 /* enable desired EVB group A interrupts */ *EVBIMRB = 0x0000。 /* clear all EVB group B interrupts */ *EVBIFRC = 0xFFFF。 /* enable desired EVA group C interrupts */ *EVBIFRA = 0xFFFF。 /* enable desired EVA group A interrupts */ *EVAIMRB = 0x0001。 /* clear all EVA group B interrupts */ *EVAIFRC = 0xFFFF。 /* enable desired core interrupts (in1,in3)*/ /*** Setup the event manager interrupts ***/ *EVAIFRA = 0xFFFF。 /* clear the IMR register */ *IFR = 0x003F。 /* configure T2CON register */ /* bit 1514 11: stop immediately on emulator suspend bit 13 0: reserved bit 1211 10: 10 = continousup count mode bit 108 111: 111 = x/128 prescaler bit 7 0: T2SWT1, 0 = use own TENABLE bit bit 6 1: TENABLE, 1 = enable timer bit 54 00: 00 = CPUCLK is clock source bit 32 00: 00 = reload pare reg on underflow bit 1 0: 0 = disable timer pare bit 0 0: SELT1PR, 0 = use own period register */ fv_ = ((num_f_d*U_DC*F_V_radio))。 /* clear timer counter */ *T2PR = timer2_per。s: reserved */ *T1CON = 0x0840。 care) bit 1110 01: PWM6/IOPB3 pin active low bit 98 10: PWM5/IOPB2 pin active high bit 76 01: PWM4/IOPB1 pin active low bit 54 10: PWM3/IOPB0 pin active high bit 32 01: PWM2/IOPA7 pin active low bit 10 10: PWM1/IOPA6 pin active high */ *COMCONA = 0x8200。 /* PWM1 pin set active high */ /* bit 15 0: space vector dir is CCW (don39。 /* set timer period */ *DBTCONA = 0x0000。 /* configure GPTCONA */ /* bit 15 0: reserved bit 14 0: T2STAT, readonly bit 13 0: T1STAT, readonly bit 1211 00: reserved bit 109 00: T2TOADC, 00 = no timer2 event starts ADC bit 87 00: T1TOADC, 00 = no timer1 event starts ADC bit 6 0: TCOMPOE, 0 = Hiz all timer pare outputs bit 54 00: reserved bit 32 00: T2PIN, 00 = forced low bit 10 00: T1PIN, 00 = forced low */ 基于 DSP 的三相異步電機(jī)控制 31 /* Timer 1: configure to clock the PWM on PWM1 pin */ /* Symmetric PWM, 20KHz carrier frequency, 25% duty cycle */ *T1CNT = 0x0000。 /* disable timer 1 */ *T2CON = 0x0000。 /* group C pins */ /* bit 15 0: reserved bit 14 0: 0=IOPF6, 1=IOPF6 bit 13 0: 0=IOPF5, 1=TCLKINB bit 12 0: 0=IOPF4, 1=TDIRB bit 11 0: 0=IOPF3, 1=T4PWM/T4CMP bit 10 0: 0=IOPF2, 1=T3PWM/T3CMP bit 9 0: 0=IOPF1, 1=CAP6 bit 8 0: 0=IOPF0, 1=CAP5/QEP4 bit 7 0: 0=IOPE7, 1=CAP4/QEP3 bit 6 0: 0=IOPE6, 1=PWM12 bit 5 0: 0=IOPE5, 1=PWM11 bit 4 0: 0=IOPE4, 1=PWM10 bit 3 0: 0=IOPE3, 1=PWM9 bit 2 0: 0=IOPE2, 1=PWM8 bit 1 0: 0=IOPE1, 1=PWM7 bit 0 0: 0=IOPE0, 1=CLKOUT */ /*** Configure IOPF5 pin as an output ***/ *PFDATDIR = *PFDATDIR | 0x2020。 /* group A pins */ /* bit 15 0: 0=IOPB7, 1=TCLKINA bit 14 0: 0=IOPB6, 1=TDIRA bit 13 0: 0=IOPB5, 1=T2PWM/T2CMP bit 12 0: 0=IOPB4, 1=T1PWM/T1CMP bit 11 1: 0=IOPB3, 1=PWM6 bit 10 1: 0=IOPB2, 1=PWM5 bit 9 1: 0=IOPB1, 1=PWM4 bit 8 1: 0=IOPB0, 1=PWM3 bit 7 1: 0=IOPA7, 1=PWM2 bit 6 1: 0=IOPA6, 1=PWM1 bit 5 0: 0=IOPA5, 1=CAP3 bit 4 0: 0=IOPA4, 1=CAP2/QEP2 bit 3 0: 0=IOPA3, 1=CAP1/QEP1 bit 2 0: 0=IOPA2, 1=XINT1 bit 1 0: 0=IOPA1, 1=SCIRXD bit 0 0: 0=IOPA0, 1=SCITXD */ *MCRB = 0xFE00。 /* bit 1511 039。 /* bits 158 039。s: reserved bit 5 0: do NOT clear the WD OVERRIDE bit bit 4 0: XMIF_HIZ, 0=normal mode, 1=HiZ39。 0x000F。 */ /****************************** MAIN ROUTINE ***************************/ void ini(void) { /*** Configure the System Control and Status registers ***/ *SCSR1 = 0x00FD。 /*unsigned int T4_NUM0=0。*/ unsigned int i=0。 unsigned int I_result[I_LOOP/I_DIV]。 /*** Constant Definitions ***/ define PI extern float sin_table[99]。 unsigned int index_pwm=0。 } include include include unsigned int period。i500000。 }