【正文】 the remainder of the register is assumed to contain zero. The PSR contains the four stored status bit values Z,N,C,and V in positions 3 through 0, respectively. In additional, a stored interrupt enable bit EI appears in position 4. Table 101 contains the 42 operations performed by the instructions. Each operation has a mnemonic and a carefully selected opcode. The operations are divided into four groups based on the number of explicit operands and whether the operation is branch. In addition, the status bits affected by the operation are listed. 12 Figure 102 gives the instruction formats for the CPU. The generic instruction format has five fields. The first, OPCODE, specifies of the operation. The next two, MODE and S , are used to determine the addresses of the operands. The last two fields, SRC and DST, are the 3bit source register and destination register address fields, respectively. In addition, there is an optional second word W that appears with some instructions as an operand or an address, but not with others. The first two bits of OPCODE, IR(15:14), determine the number of explicit operands and how the fields of the format are used. When these bits are 00,either no operand is required or the location of the operand is implied by OPCODE. Only the OPCODE field is needed, as shown in figure 2(b).the four rightmost OPCODE bits can specify up to 16 operands or with implied operand addresses. If IR(15:14) is 01, the instruction has one operand and is a data transfer or data manipulation instruction. Since there is an operand, the MODE field specifies the addressing mode for obtaining it. The single address may involve the DST register address in its formation, so the DST field is also present. The S field and SRC field relate to the presence of two operands and so are not used for the typical single operand instructions. but, the shift instructions require a shift amount to indicate how many bits to shift. For maximum flexibility, this shift amount is treated just like a source operand. As a consequence, the SHA and S fields is a full 16bit operand, but only values 0 through 15 are meaningful. There are sufficient OPCODE bits for 16 instructions with a single operand. Table 102 gives the addressing modes specified by the MODE field. The first two bits of MODE specify four different types of addressing: register, immediate, indexed, and relative to the PC. The third bit of MODE specifies whether the address generated by these modes is 13 used as an indirect address. The one exception to this is direct addressing, which is obtained by applying indirection to the immediate type. Otherwise, if the third bit equals 0, indirect addressing does not apply whereas, if it equals 1, indirect addressing does apply. For the register type of instruction, MONE(2:1)=00 and the W word is not needed. Since the operand or address es from a register. The third column of the table provides register transfer statements for each of the addressing modes for the oneoperand instructions. If IR(15:14) is equal to 10, then the instruction has two addresses used for true operands. All fields of the generic instruction, including S and SRC, are used for this case for all instructions. one of addresses, either the source or the destination, uses the addressing modes. If S=0, then the source uses the addressing mode specified by MODE, and the source is a register. If S=1, then the destination uses the addressing mode, and the source is a register. Register transfer descriptions of the resulting addresses are given in the fourth and fifth columns of Table 2. Again, depending on the contents of the MODE field, the second instruction word W, which is an address or an immediate operand, may or may not be present. Instructions with IR(15:14)=11 are branches. Aside form the S field and the SHA field for shifts, the format is the same as for IR(15:14)=01. For all instructions of this type, the destination address (not the operand) bees the new address placed in the program counter PC. As a consequence, the register mode is invalid for branch instructions. Before proceeding to the next step, which defines the datapath to support the instruction set architecture, we will briefly note the characteristics of the architecture that define it as CISC or RISC. Most of the operations given in Chapter 9 are included in the instruction set. A number of operations that do not appear are redundant. The same actions can be achieved by using proper addressing modes with instructions that do appear. For example, LD, ST, IN, and OUT can all be achieved by using MOVE instructions in a memorymapped structure. By looking at the formats for the instructions, we find that most of the instructions can operate directly on operate directly on operands from memory. There are eight addressing modes and two different lengths of instruction formats. In addition, some of the instructions perform plex operations which can be viewed as operations that are likely to take more than one clock cycle for the execution step. These characteristics clearly identify this as a CISC architecture. Datapath organization Rather than beginning from scratch, we will reuse the nonpipelined datapath employed with the microprogrammed control in section 810, with modifications. That datapath was shown in section 810, and the new, modified datapath based on it is given in Figure 106. we treat each modification in turn, beginning with the register file. In section 810, register R8 was used as a temporary storage location. In the new 14 microprogrammed architecture, there are plex instructions spanning many clock cycles and performing plicated operations. Thus, more temporary storage is needed for use by the microprograms. To meet this need, we expand the register file from 9 registers to 16. the first 8 regi