【正文】 進(jìn)。很多人認(rèn)為這才是 Intel 應(yīng)該做的。 AMD 已經(jīng)定義了一種 64 位的與 x86 更加兼容的指令集，并且他 們已經(jīng)取得了進(jìn)展。在聽到他說問題出現(xiàn)在 Intel 內(nèi)部也許有所不同，我很不理解。 由于以上的復(fù)雜因素， IA64 的實(shí)現(xiàn)需要更大的體積相對與傳統(tǒng)的指令集，這暗示著更大的消耗。很難弄懂它所指的是什么。這打亂了傳統(tǒng)的在指令字長和信息內(nèi)容的平衡，并且它改變了編譯器作者的原先的大綱。 進(jìn)一步說， IA64 的設(shè)計(jì)與其他所有的指令集在主要實(shí)現(xiàn)方式上有所不同。在這種情況下，隨后出現(xiàn)了 MIPS R4000和 Alpha。請參考特殊計(jì)算機(jī)體系構(gòu)造，第三版， 2020， P146， 1514，1578 IA64 指令集 很久以前， Intel 和 HewlettPackard 引進(jìn)了 IA64 指令集。當(dāng)致命的異常發(fā)生時， X86 引入的代碼是，經(jīng)過適當(dāng)?shù)拇鄹暮螅晦D(zhuǎn)化為它的內(nèi)部代碼并且被 RISC芯片處理。因此，設(shè)計(jì)者們沒有完全實(shí)現(xiàn) RISC 指令集，盡管這不是很明顯。 對于 x86 取得勝利的最后有一件有意思的事情。有一個已經(jīng)取得了更大的成功，我所說的 i860(不是 i960,它們有一些不同 )。我們?nèi)孕枰粩嗵嵝盐覀冏约海何覀儜?yīng) 該嚴(yán)格的與先前的應(yīng)用在機(jī)器層面上保持兼容。毫無疑問，商業(yè)上對于 x86 的生存會有更多的考慮，但是這里還有很多原因，盡管我們多么希望人們考慮其他的方面。被認(rèn)為是相當(dāng)成功的 RISC 指令集現(xiàn)在的生存空間越來越小了。INTEL 8086 及其后裔都與 x86 密切相關(guān)。隨后，計(jì)算機(jī)設(shè)計(jì)者變的多些可理性少了一些藝術(shù)性。通過模擬該設(shè)計(jì)， RISC 的提倡者能夠有信心的預(yù)言，一臺使用和傳統(tǒng)計(jì)算機(jī)相同電路的 RISC 計(jì)算機(jī)可以和傳統(tǒng)的最好的計(jì)算機(jī)有同樣的性能。 RISC 受益于一個最近的可用的方法的誕生，該方法使估計(jì)計(jì)算機(jī)性能成為可能而不去真正實(shí)現(xiàn)該微機(jī)的設(shè)計(jì)。從某種意義上說，它推動了線程的發(fā)展，在處理器中，同一時間有幾個 指令在不同的執(zhí)行階段稱為線程。該運(yùn)動是由 Patterson 和 Ditzel 發(fā)表了一篇命名為精簡指令計(jì)算機(jī)的情況論文而引起的。很少的測試方法被建立，總的來說特性的選取很大程度上依賴于設(shè)計(jì)者的直覺。是 7400 的高可靠性給了我們勇氣，使得我們著手 Cambridge Ring.項(xiàng)目。在這兩種系統(tǒng)出現(xiàn)之前，人們大多滿足于基于電報(bào)交換機(jī)的本地局域網(wǎng)。 7400 在 70 年代中期還不斷發(fā)展壯大，并且被寬帶局域網(wǎng)的先驅(qū)組織Cambridge Ring 所采用。大學(xué)或各地的研究者，可以充分發(fā)揮他們的想象力構(gòu)造任何微機(jī)可以連接的數(shù)字設(shè)備。 硬件的研究 我所描述的時代對于從事計(jì)算機(jī)硬件研究的人們是令人驚奇的時代。這就是我在概要中提到的“通貨膨脹”在計(jì)算機(jī)工業(yè)中走上了歧途之說。微機(jī)的出現(xiàn)解決了這個局面。一個商 業(yè)部門或大學(xué)有能力擁有一臺小型機(jī)而不是得到一臺大型組織所需昂貴的大型機(jī)。它被稱為小型機(jī)。他們可通過導(dǎo)線連接在一起，作成一個計(jì)算機(jī)或其他的東西。由此出現(xiàn)了我們所知道 7400 系列微機(jī)。 小規(guī)模集成電路和小型機(jī) 很快，在一個硅片上可以放不止一個晶體管，由此集成電路誕生了。他們必須忘記他們熟悉的電路 重新開始。 綜上所述，晶體管開始代替正空管。這些我認(rèn)為歸因與高級語言的起步和第一個操作系統(tǒng)的誕生。 60 年代的鞏固階段 60 年代初，個人英雄時代結(jié)束了，計(jì)算機(jī)真正引起了重視。由于動力工程師們做 事的方式與我們不同，我們也遇到了許多困難。 在最初的幾年， IEE（電子工程師協(xié)會）仍然由動力工程占據(jù)主導(dǎo)地位。舉例來說，我可以使用真空二級管做為門電路，就象在 EDSAC 中一樣，或者在兩個柵格之間用帶控制信號的五級管，這被廣泛用于其他系統(tǒng)設(shè)計(jì)，這類的選擇一直在持續(xù)著直到邏輯門電路開始應(yīng)用。最重要的是瞬態(tài)一定要小心應(yīng)付，雖然它只會在電視機(jī)的熒幕上一起一個無害的閃光，但是在計(jì)算機(jī)上這將導(dǎo)致一系列的 錯誤。我們在電子工程方面都有著豐富的經(jīng)驗(yàn)，并且我們深信這些經(jīng)驗(yàn)對我們大有裨益。 Insulating layers in the most advanced chips are now approaching a thickness equal to that of 5 atoms. Beyond finding better insulating materials, and that cannot take us very far, there is nothing we can do about this. We may also expect to face problems with onchip wiring as wire cross sections get smaller. These will concern heat dissipation and atom migration. The above problems are very fundamental. If we cannot make wires and insulators, we cannot make a puter, whatever improvements there may be in the CMOS process or improvements in semiconductor materials. It is no good hoping that some new process or material might restart the merrygoround of the density of transistors doubling every eighteen months. I said above that there is a general expectation that shrinkage would continue by one means or another to 45 nm or even less. What I had in mi nd was that at some point further scaling of CMOS as we know it will bee impracticable, and the industry will need to look beyond it. Since 2020 the Roadmap has had a section entitled emerging research devices on nonconventional forms of CMOS and the like. Vigorous and opportunist exploitation of these possibilities will undoubtedly take us a useful way further along the road, but the Roadmap rightly distinguishes such progress from the traditional scaling of conventional CMOS that we have been used to. Advances in Memory Technology Unconventional CMOS could revolutionalize memory technology. Up to now, we have relied on DRAMs for main memory. Unfortunately, these are only increasing in speed marginally as shrinkage continues, whereas processor chips and their associated cache memory continue to double in speed every two years. The result is a growing gap in speed between the processor and the main memory. This is the memory gap and is a current source of anxiety. A breakthrough in memory technology, possibly using some form of unconventional CMOS, could lead to a major advance in overall performance on problems with large memory requirements, that is, problems which fail to fit into the cache. Perhaps this, rather than attaining marginally higher basis processor speed will be the ultimate role for nonconventional CMOS. Shortage of Electrons Although shortage of electrons has not so far appeared as an obvious limitation, in the long term it may bee so. Perhaps this is where the exploitation of nonconventional CMOS will lead us. However, some interesting work has been by Haroon Amed and his team working in the Cavendish the direct development of structures in which a single electron more or less makes the difference between a zero and a one. However very little progress has been made towards practical devices that could lead to the construction of a puter. Even with exceptionally good luck, many tens of years must inevitably elapse before a working puter based on single electron effects can be contemplated. 微機(jī)發(fā)展簡史 IEEE 的論文 劍橋大學(xué)， 2020/2/5 莫里斯 威爾克斯 計(jì)算機(jī)實(shí)驗(yàn)室 劍橋大學(xué) 第一臺存儲程序的計(jì)算開始出現(xiàn)于 1950 前后，它就是 1949 年夏天在劍橋大學(xué)，我們創(chuàng)造的延遲存儲自動電子計(jì)算機(jī)（ EDSAC）。A cyclist sets out on a circular cycling tour. Derive an equation giving the direction of the wind at any time. The singlechip puter At each shrinkage the number of chips was reduced and there were fewer wires going from one chip to another. This led to an additional increment in overall speed, since the transmission of signals from one chip to another takes a long time. Eventually, shrinkage proceeded to the point at which the whole processor except for the caches could be put on one chip. This enabled a workstation to be built that outperformed the fastest miniputer of the day, and the result was to kill the miniputer stone dead. As we all know, this had severe consequences for the puter industry and for the people working in it. From the above time the high density CMOS silicon chip was Cock of the Roost. Shrinkage went on until millions of transistors could be put on a single chip and the speed went up in proportion. Processor des