【正文】 集電極在內(nèi)部被連接到外殼上，因此，與集電極的連接要通過一個裝配螺栓或外殼底面。更復(fù)雜的集成電路（ ICs）用不同形狀的外殼包裝，例如平面包裝。使人容易搞亂的問題是同一 TO 號碼的子系列產(chǎn)品其管腳位置是不一樣的 。 TO1 是一種最早的晶體管外殼 即一個在底部帶有三個引腳的圓柱體 “ 外罩 ” ，這三個引腳在底部形成三角狀。 在 NPN 型晶體管中，工作原理完全相同，但是兩個電源的極性正好相反（圖12B4）。在上述的 PNP 型晶體管中，發(fā)射極電壓必須為正。 在這種工作方式中，基極 發(fā)射極電路是輸入側(cè)；通過基極的發(fā)射極和集電極電路是輸出側(cè)。）這是晶體管最常見的連接方式，但是，當(dāng)然也存在其它兩種連接方法 共基極 連接和共集電極連接。這些電子被頂部 P 區(qū) 接收，因此它被稱為集電極，但是流過這個特定電路實際電流的大小由加到中間層的偏置電壓控制，所以中間層被稱為基極。在加正向偏置電壓的情況下，如圖 12B2所示的 PNP 晶體管，電流從底部的 P極流到中間的 N極。事實上，保留這個外部電壓并去掉上半部分，晶體管將會象二極管一樣工作。因為晶體管包含兩個不同極性的區(qū)域（例如 “ P”區(qū)和“ N”區(qū)），所以晶體管被叫作雙向器件，或雙向晶體管。由 N型摻雜和 P 型摻雜處理的鍺或硅的單晶體可形成半導(dǎo)體二極管，它具有我們描述過的工作特性。 1) 第一個定律指出：在一般運(yùn)算放大器電路中，可以假設(shè)輸入 端間的電壓為零，也就是說， U+ =U 2) 第二個定律指出：在一般運(yùn)算放大器電路中，兩個輸入電流可被假定為零： I+ =I =0 第一個定律是因為內(nèi)在增益 A的值很大。這是運(yùn)算放大器設(shè)計的重要特征之 在信號作用下，電路的動作僅取決于能夠容易被設(shè)計者改變的外部元件，而不取決于運(yùn)算放大器本身的細(xì)節(jié)特性。各個電流定義如圖12A2 中的 b 圖所示。第三個重要的設(shè)計特點就是運(yùn)算放大器的輸出阻抗 (R0)非常小。 集成電路技術(shù)使得在非常小的一塊半導(dǎo)體材料的復(fù)合 “芯片 ” 上可以安裝許多放大器電路。每一個電壓均指的是相對于接零管腳 的電位。圖中只給出三個管腳：正輸入、負(fù)輸入和輸出。因此，運(yùn)算放大器對于在不同技術(shù)領(lǐng)域中需要使用簡單放大器而不是在晶體管級 做設(shè)計的研究人員來說是非常有用的。就此而言，我們不再描述這些元件的內(nèi)部工作原理。、β、 Ri、 R0等 )的內(nèi)部特性。 is the base, the one to the fight (marked by a color spot) the collector and the one to the left the emitter.[2] The collector lead may also be more widely spaced from the base lead than the emitter lead. In other TO shapes the three leads may emerge in similar triangular pattern (but not necessarily with the same positions for base, collector and emitter), or inline. Just to confuse the issue there are also subtypes of the same TO number shape with different lead designations. The TO92, for example, has three leads emerging in line parallel to a flat side on an otherwise circular 39。 for negative in the case of an NPN transistor). This is also inferred by the reverse direction of the arrow on the emitter in the symbol for an NPN transistor, ., current flow away from the base. While transistors are made in thousands of different types, the number of shapes in which they are produced is more limited and more or less standardized in a simple code TO (Transistor Outline) followed by a number. TO1 is the original transistor shape a cylindrical 39。 and the emitter through base to collector circuit the output side. Although these have a mon path through base and emitter, the two circuits are effectively separated by the fact that as far as polarity of the base circuit is concerned, the base and upper half of the transistor are connected as a reverse biased diode. Hence there is no current flow from the base circuit into the collector circuit. For the circuit to work, of course, polarities of both the base and collector circuits have to be correct (forward bias applied to the base circuit, and the collector supply connected so that the polarity of the mon element (the emitter) is the same from both voltage sources). This also means that the polarity of the voltages must be correct for the type of transistor. In the case of a PNP transistor as described, the emitter voltage must be positive. It follows that both the base and collector are negatively connected with respect to the emitter. The symbol for a PNP transistor has an arrow on the emitter indicating the direction of current flow, always towards the base. (39。N39。holes39。s law to find the voltage at the negative input, U, noting the assumed current direction and the fact that ground potential is zero volts: (U0)/ R1=I So, U=IR1 and from Eq. (12A3), U =[R1/(R1+R2)] U0 Since we now have expressions for U+ and U, Eq. (12Al) may be used to calculate the output voltage, U0 = A（ U+U） =A[USR1U0/(R1+R2)] Gathering terms, U0 =[1+AR1/(R1+R2)]= AUS (12A4) and finally, AU = U0/US= A(R1+R2)/( R1+R2+AR1) (12A5a) This is the gain facto