【導(dǎo)讀】Mnemonic(助記符):①Assemblylanguage;②machinelanguage;③High-levellanguage;④

　　

【正文】 . 問題 18 PC (program counter) belongs to ( ). A. memory B. ALU C. I/O D. controller 問題 19 In CPU, the register storing the current instruction being executed is___IR____， pointing to the next instruction to be fetched is__PC____. 問題 20 Generally, serial register has the function of shift operation. 問題 21 The register used to store the current instruction being executed is IR. 問題 22 In CPU, register__MAR__ is used to store the memory address during READ/WRITE operations. Register__SR____ is used to store the status bits as the result of execution of arithmetic, logic and testing instruction. 問題 23 CPU does not includes ( ). A. MAR B. address decoder C. IR D. instruction decoder 問題 24 If the frequency of a puter is the highest, then its speed is the fastest. 問題 25 For a nbit CPU, n means__數(shù)據(jù)邏輯總線數(shù)為 n___ 第九章 問題 1 Which unit is responsible for decode ( ). A .controller D .ALU 問題 2 In micro programmed controller, control unit send control signals to execute unit, the control signals are called ( ) A. micro mands B. micro operations C .micro program D. micro instructions 問題 3 Each machine instruction is interpreted and executed by a microcode consisting of a sequence of microinstructions A .對(duì) B. 錯(cuò) 問題 4 The function(s) of control unit is(are) ( ) A .to fetch an instruction from memory B .to decode the OPcode of an instruction C .to generate sequential signals D to fetch instruction from memory and decode and generate corresponding control signals and execute 問題 5 The instruction cycle for all the operations is the same A .對(duì) B .錯(cuò) 問題 6 Mutually exclusive microoperations are the operations that cannot execute parallel in a CPU cycle A .對(duì) B .錯(cuò) 問題 7 In micro programmed controller, the relationship between machine instruction and micro instruction is machine instruction is interpreted and executed by micro program which constitutes of some micro instructions B .a micro instruction is posed of some machine instruction C. each machine instruction is executed by one micro instruction D. a program constitutes of some machine instructions can be implemented by a micro instruction. 問題 8 CPU cycle is also called clock cycle. A CPU cycle consists of some machine cycles A .對(duì) B .錯(cuò) 問題 9 The mircomands of a microinstruction is mutually exclusive, then ( ). A .they are faulttolerance B. they can replace each other C. they can appear in the same time D .they cannot appear in the same time 問題 10 Processer adopts micro programmed controller is called micro processer. A .對(duì) 問題 11 Instruction cycle is the time that CPU fetches an instruction from memory and executes it 問題 12 Every instruction cycle needs at least 2 CPU cycles. 問題 13 Microprogram utilizes software method to design the control operations. A .對(duì) 問題 14 Instruction cycle is（ ） time for reading and executing an instruction B. the time for executing an instruction C. the time for reading an instruction from memory D .clock cycle 問題 15 The basic idea of multiple transfer for fetch the address of the next microinstruction is（ ） A .using PC B .using μPC C. using judge field(控制字段 ) of μPC D .using a specific field in instruction 問題 16 Machine cycle is defined by（ ） A .the minimal time for reading an instruction word from memory B .the average time for writing a data word to memory C .the maximal time for reading a data word from memory D .the average time for reading a data word to memory 問題 17 Comparing to microprogram controller, hardwired controller are: A .low in execution, hard for modify and extend of instruction function B .fast in execution, easy for modify and extend of instruction function C. fast in execution, hard for modify and extend of instruction function D .low in execution, easy for modify and extend of instruction function. 問題 18 Instruction cycle is also called CPU cycle A 對(duì) B .錯(cuò)誤 問題 19 Microprograms are stored in（ ） memory B main memory C RAM D IRs 問題 20 The hardwired controller run low and it is hard to modify and extend A 對(duì) B 錯(cuò)誤 第七題和 22 題錯(cuò)了，是因?yàn)榭墒清e(cuò)了但是答案是對(duì)的 16K*1bit memory chips to form 64K*8bit main memory module. It need expand 錯(cuò)誤 !未找到引用源。 times in word, expand 錯(cuò)誤 !未找到引用源。 times in bit. multilevel hierarchical structure of a puter memory system, 錯(cuò)誤 !未找到引用源。 is the fastest, 錯(cuò)誤 !未找到引用源。 is the lowest.( 具 體 答 案 不 知 通 用 寄 存 器 脫 機(jī) 外 部 存 儲(chǔ) 器 道 ) word length of a puter is 32 bit, the capacity of the memory is 64MB. If the memory is addressed by word, then its range of addressing is 錯(cuò)誤 ! 未 找 到 引 用 源 。 ~ 錯(cuò)誤 ! 未 找 到 引 用源。 .22Let the word length of a puter is 32 bit, the capacity of the memory is 4MB. If the memory is addressed by half word, then its addressing space is 錯(cuò)誤 !未找到引用源。 .（格式錯(cuò)了但是范圍是對(duì)的） a puter system, all the following units can store information： ① Primary memory。 ② general registers in CPU。 ③cache ④ magic tape ⑤ disk. According to access speed, the order by fast to low is 錯(cuò)誤 !未找到引用源。 . Main memory includes 錯(cuò)誤 !未找到引用源。 ； Secondary memory includes ④⑤ mapping functions between main memory and cache use fullassociative mapping scheme, direct mapping scheme and setassociative mapping scheme.( 對(duì) )