【正文】 Delivery for PostCMP Cleaning DI water and chemical Porous brush Redrawn from D. Hynes, et al, “Brush Scrubbing Emerges as Future WaferCleaning Technology, Solid State Technology, (July 1997): p. 210. Figure 169。 2023 by Prentice Hall Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda Examples of Some Commercial CMP Equipment Systems S u p p l i e r / M o d e lTyp e o fM o ti o nN o . o fP l ate n s / D i a .(i n . ) o f Waf e rC ar r i e r s (o rh e ad s )D r yI n /D r yO u tEn d p o i n tD e te c ti o nA p p l i e d M at e r i al s M i rr a 340 0 Ro t a r y 3 / 20 ” 4 Y e s Y e sEb ar a E P O 222 Ro t a r y 2 / 23 . 6” 1 Y e s Y e sS p e e d fam I P EC A v a n t i 472 A v a n t i 672 IP E C 676/ 776 A u ri ga CO r b i t a lO r b i t a lO r b i t a lRo t a r y2 / 22 . 5”3 o r 6 / 32”4 / 16 ”13 o r 64Y e sY e sY e sY e sY e sY e sLam T e r e s L i n e a r 2 b e l t s 4 Y e s Y e sS p e e d F am A u ri ga O r b i t a l 2 / 32 ” 5 Y e s Y e sS tr as b au gh S y m ph o n y Ro t a r y 3 / 32 ” 4 Y e s Y e sTable 169。 2023 by Prentice Hall Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda CMP Applications ? STI oxide polish ? ILD1 oxide polish ? LI tungsten polish ? ILD oxide polish ? Tungsten plug polish ? Dual Damascene copper polish 169。 2023 by Prentice Hall Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda CMP for Oxide Fill of STI 1Planari zation b y che m ica l m ech ani cal p ol ish in gSTI oxide after poli shLiner oxi dep+ Sil ico n sub st rat ep Epit axi al l aye rnw el l pw el lNit r ide st rip3Oxide CVD2Figure 169。 2023 by Prentice Hall Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda LI Oxide before and after CMP Planarization nwe ll pwe llOxi de CMP 3LI oxi dep+ Sil ico n sub str at ep Epit axi al lay er2 Dope d o xide CV D1 Ni tr ide C VDFigure 169。 2023 by Prentice Hall Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda ILD Oxide Polish Oxi de CMPILD 1 oxide etc hp+ Sil ico n sub str at ep Epit axi al lay ernwe ll pwe ll23LI oxi deILD 1 ox id e d ep osi tion1ILD1Figure 169。 2023 by Prentice Hall Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda CMP for Dual Damascene Copper Metallurgy 2 C u de po s it io n3 Cu /T a/n i tride /o xide CM PO x id e1 T a de po s it io nT an ta lu mC op pe rN it ri deFigure 169。 2023 by Prentice Hall Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda Results of CMP MicroScratch 3) Tungsten CMP SiO2 Tungsten plug Short circuit between two tungsten plugs 2) Via etch followed by tungsten via fill Tungsten 1) SiO2 deposition followed by CMP Metal1 stack Microscratch ILD1 SiO2 ILD2 Figure 169。 2023 by Prentice Hall Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda Chapter 18 Review ? Quality Measures 538 ? Troubleshooting 540 ? Summary 541 ? Key Terms 541 ? Review Questions 542 ? Equipment Supplier Web Sites 542 ? References 543 169。 2023 by Prentice Hall Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda 謝謝觀看 /歡迎下載 BY FAITH I MEAN A VISION OF GOOD ONE CHERISHES AND THE ENTHUSIASM THAT PUSHES ONE TO SEEK ITS FULFILLMENT REGARDLESS OF OBSTACLES. BY FAITH I BY FAITH