【正文】 a reserved 8bit code (00000XXX). In such cases, the bridge remains closed and the transfer proceeds in F/Smode. Table 3 gives the possible munication speeds in such a system. Bus system with transfer at Hs and F/Smode speeds(1) Bridge not used. SDA and SCL may have an alternative function.(2) To input filter.(3) Only the active master can enable its currentsource pullup circuit.(4) Dotted transistors are optional opendrain outputs which can stretch the serial clock signal SCL or SCLH.Table 3 Communication bitrates in a mixed speed bus system F/SMODE TRANSFER IN A MIXEDSPEED BUS SYSTEMThe bridge shown in interconnects corresponding serial bus lines, forming one serial bus system. As no master code (00001XXX) is transmitted, the currentsource pullup circuits stay disabled and all output stages are opendrain. All devices, including Hsmode devices, municate with each other according the protocol, format and speed of the F/Smode I2Cbusspecification. HSMODE TRANSFER IN A MIXEDSPEED BUS SYSTEMFigure 25 shows the timing diagram of a plete Hsmode transfer, which is invoked by a START condition, a master code, and a notacknowledge A (at F/Smode speed). Although this timing diagram is split in two parts, it should be viewed as one timing diagram were time point tH is a mon point for both parts. A plete Hsmode transfer in a mixedspeed bus system.The master code is recognized by the bridge in the active or nonactive master (see ). The bridge performs the following actions:1. Between t1 and tH (see ), transistor TR1 opens to separate the SDAH and SDA lines, after which transistor TR3 closes to pulldown the SDA line to VSS.2. When both SCLH and SCL bee HIGH (tH in ), transistor TR2 opens to separate the SCLH and SCL lines. TR2 must be opened before SCLH goes LOW after Sr.Hsmode transfer starts after tH with a repeated START condition (Sr). During Hsmode transfer, the SCL line stays at a HIGH and the SDA line at a LOW steadystate level, and so is prepared for the transfer of a STOP condition (P).After each acknowledge (A) or notacknowledge bit (A) the active master disables its currentsource pullup circuit. This enables other devices to delay the serial transfer by stretching the LOW period of the SCLH signal. The active master reenables its currentsource pullup circuit again when all devices are released and the SCLH signal reaches a HIGH level, and so speeds up the last part of the SCLH signal’s rise time. In irregular situations, F/Smode devices can close the bridge (TR1 and TR2 closed, TR3 open) at any time by pulling down the SCL line for at least 1 ms, . to recover from a bus hangup.Hsmode finishes with a STOP condition and brings the bus system back into the F/Smode. The active master disables its currentsource MCS when the STOP condition (P) at SDAH is detected (tFS in ). The bridge also recognizes this STOP condition and takes the followingactions:1. Transistor TR2 closes after tFS to connect SCLH with SCL。 both of which are HIGH at this time. Transistor TR3 opens after tFS, which releases the SDA line and allows it to be pulled HIGH by the pullup resister Rp. This is the STOP condition for the F/Smode devices. TR3 must open fast enough to ensure the bus free time between the STOP condition and the earliest nextSTART condition is according to the Fastmode specification (see tBUF in Table 5).2. When SDA reaches a HIGH (t2 in ) transistor TR1 closes to connect SDAH with SDA. (Note:interconnections are made when all lines are HIGH, thus preventing spikes on the bus lines). TR1 and TR2 must be closed within the minimum bus free time according to the Fastmode specification (see tBUF in Table 5). TIMING REQUIREMENTS FOR THE BRIDGE IN AMIXEDSPEED BUS SYSTEMIt can be seen from that the actions of the bridge at t1, tH and tFS must be so fast that it does not affect the SDAH and SCLH lines. Furthermore the bridge must meet the related timing requirements of the Fastmode specification for the SDA and SCL lines.